HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 53

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

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Name
INT_M1
Name
INT_M2
Name
TRM
For mask bits a '1' enables and a '0' disables interrupt. RESET clears all bits to '0'.
For mask bits a '1' enables and a '0' disables interrupt. RESET clears all bits to '0'.
Addr.
Addr.
Addr.
1Ah
1Bh
12h
Bits
Bits
Bits
7..6
1..0
4..2
0
1
2
3
4
5
6
7
0
1
2
3
4
5
5
6
7
r/w Function
r/w Function
r/w Function
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
interrupt mask for channel B2 in transmit direction
interrupt mask for channel D in transmit direction
interrupt mask for channel B1 in receive direction
interrupt mask for channel B2 in receive direction
interrupt mask for channel D in receive direction
interrupt mask for state change of TE/NT state machine
interrupt mask for timer
interrupt mask for processing/non processing phase transition
interrupt mask for GCI I-change
interrupt mask for GCI monitor receive
enable for interrupt output ('1' = enable)
interrupt output is reversed
interrupt from external device is reversed
unused
FIFOs or Z2 in transmit FIFOs change from:
00: x xxxx x011 1111
01: x xxxx 0111 1111
10: x xxx0 1111 1111
11: x 0111 1111 1111
E
When set the E receive channel of the S/T interface is
connected to the B2 receive channel.
B1+B2 mode
'0' normal operation (reset default)
'1' B1+B2 are combined to one HDLC or transparent channel.
IOM test loop
When set MST output data is looped to the MST input.
interrupt mask for channel B1 in transmit direction
interrupt in transparent mode is generated if Z1 in receive
must be '0'
All settings for data shape and connect are derived from
B1.
B2 receive channel
x xxxx x100 0000
x xxxx 1000 0000
x xxx1 0000 0000
x 1000 0000 0000
Cologne
Chip
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