HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 43

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

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4
4.1
4.2
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Name
FIF_SEL
Name
STATES
(read)
STATES
(write)
Register bit description
Register bit description of the FIFO select register
Register bit description of S/T section
Addr.
Addr.
10h
30h
30h
Bits
Bits
2..0
6..3
3..0
3..0
6..5
7
4
5
6
7
4
7
r/w Function
r/w Function
w
w
w
w
w
w
r
r
r
r
r
select FIFO and operation
bit 2
0
0
0
0
1
1
unused, should be '0'
select data transmission bit order
'0'
'1'
binary value of actual state (NT: Gx, TE: Fx)
Frame-Sync ('1'=synchronized)
'1' timer T2 expired (NT mode only, see also 8.1 S/T interface
'1' receiving INFO0
'0' no operation
'1' in NT mode allows transition from G2 to G3.
This bit is automatically cleared after the transition.
binary value of new state (NT: Gx, TE: Fx)
(bit 4 must also be set to load the state).
'1' loads the prepared state (bit 3..0) and stops the state
'0' enables the state machine (bits 3..0 are ignored).
'00' no operation
'01' no operation
'10' start deactivation
'11' start activation
The bits are automatically cleared after activation/deactivation.
'0' no operation
'1' in NT mode allows transition from G2 to G3.
This bit is automatically cleared after the transition.
activation/deactivation layer 1 for finite state matrix for NT
on page 71)
machine.This bit needs to be set for a minimum period of
5.21 s and must be cleared by software. (reset default)
After writing an invalid state the state machine goes to
deactivated state (G1, F2)
normal read/write data operation
reverse bit order read/write data operation
bit 1
0
0
1
1
x
x
bit 0
0
1
0
1
0
1
selected operation
B1 transmit
B1 receive
B2 transmit
B2 receive
D transmit
D receive
Cologne
Chip
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