HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 17

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

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3
3.1
ISA-PC mode is selected by MODE = NC, ALE = GND and IIOSEL0..3 0.
The HFC-SP occupies two consecutive addresses in the I/O map of a PC if it is in ISA-PC mode. It
decodes only the 10 lower address lines as most slot cards do on the ISA-PC bus. The base I/O address is
2 byte aligned so the lower of both addresses is the one with SA0 = 0 and the higher address is the one
with SA0 = 1.
After every hardware reset (RESET = 1) the I/O address select circuit inside the HFC-SP is in hardware
mode. In this mode the HFC-SP can not be accessed until it is initialised to an I/O address.
At first one of 15 different I/O addresses must be selected by the 4 inputs IIOSEL0 .. IIOSEL3 as Table 2
shows:
Table 2: Selected I/O address after reset
The hardware selected I/O address might have an address collision with another I/O device in the PC.
After a hardware reset (RESET = 1) you must first write an I/O address into the HFC-SP to set the I/O
address for every further access to the device.
The procedure is as follows:
First you must write the lower 8 bits of the new I/O address you want into the lower address (SA0 = 0) of
the hardware selected I/O address. The LSB of the new address is a don't care bit because the HFC-SP
always occupies two I/O addresses.
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Functional description
ISA-PC mode
IIOSEL
3 2 1 0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Selected I/O address
processor mode
2D0h
2E0h
2C0h
2E8h
2B0h
3E0h
3E8h
210h
200h
2F8h
320h
278h
310h
330h
300h
Cologne
Chip
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