AN1836-AN21161 Analog Devices, AN1836-AN21161 Datasheet
AN1836-AN21161
Related parts for AN1836-AN21161
AN1836-AN21161 Summary of contents
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Interfacing the ADSP-21161 SIMD SHARC DSP to the AD1836 (24-bit/96kHz) Multichannel Codec Example Interface Drivers in Assembly and C For Use With The 21161 EZ-KIT-LITE S/PDIF Receiver a ADC1 DAC1 a ADC2 DAC2 ...
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... ADDS-21161N EZ-KIT Lite Development Platform, which includes an AD1836, AD1852 and SP/DIF receiver as the analog/digital audio interface. I would like to also thank Dan Ledger of Analog Devices for his contribution of the AD1836 C-based Driver Source Code packed mode, etc). ...
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ADSP-2161 EZ-KIT Lite: An AD1836/ADSP-21161 Audio System Reference Design The AD1836/ADSP-21161 pairing satisfies the higher fidelity audio requirements for new emerging audio applications, and offers many advantages for a low-cost high-fidelity audio platform, including: • AD1836's TDM Serial Mode ...
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Figure 3. ADDS-21161-EZLITE Development Board Functional Block Diagram The ADDS-21161N-EZLITE evaluation contains the following components: ADSP-21161N SHARC DSP running at 100 MHz Memory 1 M-bit (on-chip memory SDRAM running at 100 MHz 512K x 8-bit Flash Memory ...
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... More audio channels The Analog Devices AD1836 offers 24-bit, 96 kHz multichannel audio capability to meet many new requirements in the professional, consumer and automotive audio markets. Multibit sigma-delta converters such as the AD1836 are capable of 24- bit resolution, capable of exceeding the dynamic range available using 16 bit conversion. The popularity of 24-bit D/As is increasing for both professional and high-end consumer applications ...
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Figure 4. Fixed Point DSP Comparisons and Their Relationship To Converter Dynamic Range/SNR Fixed-Point DSP Dynamic Range Comparisons 24-bit DSP 16,777,216 16-bit DSP Levels of Quantization 65536 Levels of Quantization 144 dB Dynamic Dynamic Range Range ...
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AD1836's D/A converters and generate audible noise for many recursive algorithms with stringent filter specifications. The same audio processing algorithm implemented on the ADSP-21161 (which is the case when porting the same ANSI C code from one ...
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R. Wilson [3] and Chen [7] demonstrated that even for recursive second order IIR filter computations on a 24-bit DSP, the noise floor of the digital filter can still go above that of the 16-bit sample and hence become audible. ...
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The complexity of DSP algorithms increases with the introduction of new audio standards and requirements, and designers are looking to 24-bit converters like the AD1836 to increase signal quality in their low-cost multichannel audio applications. To preserve the quality of ...
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... The AD1836 supports multiple I2S connections to DSP I2S ports additional mode of operation, the AD1836 TDM serial port functionality is very similar other Analog Devices SoundPort Codecs like the AD1819, AD1881 and AD1847. It’s interface can communicates with a DSP or ASIC in a time-division multiplexed (TDM) mode, where DAC/ADC data are received and transmitted in different timeslots in a TDM frame ...
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AD1836 Serial Port Clocks And Frame Sync Rates To keep clock jitter to a minimum, the AD1836 derives its clock internally from an externally attached 12.288 MHz crystal (24.576 MHz if generating 96 kHz sample rates) and drives a ...
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AD1836/ADSP21161 EXT-TDM Digital Serial Interface Protocol The Extended TDM Mode protocol described in the AD1836 data sheet provides for a 8x32bit timeslots-bit time slot. Timeslot # FSTDM (FS0) BCLK not to scale- 256 BCLKs per ABCLK (RCLK0 & TCLK2) ...
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Optional th 1/8 Inch Headphone Out Jack for DAC0 L/R TORX173 Optical Receiver CS8414 RCA Phono SSM2275 Line In Stereo JACKs Amps th Optional 1/8 Inch MIC jack for ADC0 Figure 11. ADSP-21161 EZ-KIT Lite Audio Interface (Extended TDM Mode ...
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A new audio output frame begins with a low to high transition of FSTDM. FSTDM is synchronous to the rising edge of ABCLK. On the immediately following falling edge of ABCLK, the ADSP-21161 samples the assertion of FSTDM. This falling ...
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The audio input frame (data samples sent to the DSP from the AD1836) begins with a low to high transition of FSTDM (FS0). FSTDM is synchronous to the rising edge of ABCLK (SCLK0). On the immediately following falling edge of ...
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Configuring The ADSP-21161 Serial Port Multichannel Interface When interfacing the AD1836 codec to an ADSP-21161 SHARC processor, the interconnection between the 2 devices can be through either SPORT0/2 or SPORT1/3 TDM pairs. In the application code section of this ...
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Table 1. ADSP-21161 SPORT0/2 TDM Configuration Function Function Transmit data Transmit clock Transmit frame sync/ word select Receive data Receive clock Receive frame sync NOTE: The ADSP-21161 SPORT channel B pins are not functional for multichannel mode. Both the transmitter ...
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ADSP-21161 - 3.3 V Level Shifting Considerations The ADSP-21161 is a new derivative of the ADSP-2116x SIMD SHARC family which is based on a .18 micron CMOS process, and is a dual voltage part operating at a 1.8 volt ...
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SPORT DMA Channels And Interrupt Vectors There are 8 dedicated DMA channels for SPORT0, SPORT1, SPORT2, and SPORT3 on the ADSP-21161. The IOP addresses for the DMA parameter registers are shown in the table below for each corresponding channel ...
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... SPORT0 and SPORT2. To program these registers, you write to the appropriate address in memory using the symbolic macro definitions supplied in the def21161.h file (included with the Visual DSP tools in the /INCLUDE/ directory). External devices such as another ADSP-21161 host processor, can write and read the SPORT control registers to set up a serial port DMA operation or to enable a particular SPORT ...
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SPORT0/SPORT2 IOP Register Configurations For Audio Processing At 48 kHz The configuration for SPORT0 and SPORT2, for use with the ADSP-21161 EZ-KIT Lite at a fixed 48 kHz sample rate, is set up as follows: • 32-bit serial word ...
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R0; dm(MT2CCS1) = R0; dm(MT2CCS2) = R0; dm(MT2CCS3) = R0; • Multichannel Mode - Length = 8 multichannel words enabled. This allows 1 AD1836 frame per ADSP-21161 frame. /* sport0 & sport2 receive and transmit multichannel word enable ...
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SPORT DMA Registers For The ADSP-21161 The following register descriptions are provided in the defs21161.h file for programming the DMA registers associated with the I/O processor’s DMA controller. We will next examine how these registers are programmed for DMA ...
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Setting Up The ADSP-21161 DMA Controller For Chained SPORT DMA Transfers To efficiently transmit and receive digital audio data to/from the AD1836, the recommended method is to use "Serial Port DMA Chaining" to transfer data between the serial bus ...
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Note that the count and modified values can be initialized in the buffer declaration so that they are resident after a DSP reset and boot. However, at runtime, further modification of the buffer is required to initiate the DMA autobuffer ...
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Emx (destination buffer step size), Eix (destination buffer index (initialized to start address)), GPx ("general purpose"), CPx ("Chain Point register"; points to last address (IIx) of next TCB to jump to upon completion of this TCB.), Cx (length of source ...
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AD1836 TDM Serial Port Time Slot Assignments and Their DMA Buffer Relationships The DSP SPORT Multichannel Mode Time Slot Map for AD1836 communication in Extended TDM mode is as follows: Timeslot DSDATA1 (D2A) Pin - Outgoing Data "Playback" 0 ...
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In order to provide easier reading of the AD1836 DSP assembly driver, symbolic macro definitions are defined in order to describe each offset in the DMA buffer, showing it's relationship to the actual TDM timeslot and AD1836 ADC/DAC resource. These ...
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Programming the AD1836's Slave SPI Port The AD1836 has an SPI compatible slave control port, which is a four wire serial control port. The format is similar to the Motorola SPI format. This allows the following SPI slave register ...
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Due to the current AD1836 SPI anomaly, the 21161 EZ-KIT Lite reference source codes uses the second method shown above for interfacing the the AD1836's SPI slave port. Using SPORT1 and SPORT 3 to communicate allows us to "trick" the ...
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Codec Register Addr Read 1/ Write 0 D15 D14 D13 D12 0x0 (0000) 0x1 (0001) 0x2 (0010) 0x3 (0011) 0x4 (0100) 0x5 (0101) 0x6 (0110) 0x7 (0111) 0x8 (1000) 0x9 (1001) 0xA (1010) 0xB (1011) 0xC (1100) 0xD (1101) 0xE ...
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Configuring The AD1836 Serial Link To TDM Mode For ADI SPORT Compatibility The Extended TDM Mode allows an efficient communication interface between DSP and the AD1836. This mode of operation works efficiently with the use of serial port "autobuffering" ...
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The ADSP-21161 assembly code instructions are shown below for configuring the SPORT1/SPORT3 pair for SPI emulation in order to provide the capability to program the AD1836 registers /* clear multichannel/miscellaneous control register for SPORT1 & SPORT3 */ R0 = 0x0; ...
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DSP Programming Of The AD1836 Control/Status Registers 5. Addr. Codec Register Name 0x0 DAC Control 1 0x1 DAC Control 2 0x2 DAC Volume 0 0x3 DAC Volume 1 0x4 DAC Volume 2 0x5 DAC Volume 3 0x6 DAC Volume 4 ...
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ADC2_PEAK_LEVEL | READ_REG | 0x000, ADC3_PEAK_LEVEL | READ_REG | 0x000, ADC_CONTROL1 ADC_CONTROL2 ADC_CONTROL3 5.1 Programming AD1836 Registers Using A Zero Overhead Loop Construct The following assembly language hardware DO LOOP shows how the values in the Init_Codec_Registers[ ] buffer are ...
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The IDLE instruction will tell the DSP to do nothing but wait for a SPORT3/SPI transmit interrupt after data has be written the the SPORT/SPI transmit buffer. Waiting for the SPORT/SPI interrupt will guarantee that all data in the ...
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Processing AD1836 Audio Samples via the SPORT0 RX ISR In this section we investigate example DSP instructions for processing data from the SPORT0 receive interrupt vector. The ADSP-21161 typically processes newly received serial data by servicing SPORT interrupts, which ...
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DMA buffer, where it is then transferred to the SPORT transmit data register for shifting out of the serial port. The AD1836 codec processing instructions can be executed with either the transmit ...
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... DSP memory memory, where it will be read by the SPORT0 interrupt service routine and copied into the output transmit DMA buffer. Notice that all Analog Devices supplied EZ-KIT assembly and C demos use the same standard names for input and output audio variables. The following Table 11 shows the definitions for these variables in both assembly and C and how they are related to the DMA transmit and receive buffer offsets: TABLE11 ...
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C-Style Variable Declarations C-Callable Assembly Variable Declarations in ADDS_21161_EZKIT.ASM /* AD1836 stereo-channel data holders - used for DSP processing of audio data received from codec */ // input channels .var _Left_Channel_In0; .var _Left_Channel_In1; .var _Right_Channel_In0; .var _Right_Channel_In1; .var _Left_Channel_SPDIF_rx; .var ...
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ADSP-21161 SPORT DMA & AD1836 Multichannel Timing Notes Depending on processing data from the SPORT2 transmit interrupt or SPORT0 receive interrupt, the DSP programmer should be aware of TX/RX serial interrupt timing differences process data from the ...
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Multichannel, DMA and ISR Methods of Implementation For Processing 48 kHz Data Now that we have examined in section 6.1 the relative timing difference in SPORT TX and RX interrupts between the transmit and receive channels, we will investigate ...
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... En g. Soc. 7 Inter. Conf., Toronto, Ont., Canada, May 14 [2] Analog Devices Whitepaper, ADSP-21065L: Low-Cost 32-bit Processing for High Fidelity Digital Audio, Analog Devices, 3 Technology Way, Norwood, MA, November 1997 [3] R. Wilson, “Filter Topologies”, J. Audio Engineering Society, Vol 41, No. 9, September 1993 [4] J. Dattorro, “The Implementation of Digital Filters for High Fidelity Audio”, Audio in Digital Times, Proc. Audio En g. Soc. 7 ...
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ADSP-21161 / AD1836 DSP Driver Description POWER CONNECTOR 3 Interrupt (IRQ) Buttons 4 Flag In Pushbuttons 6 Flag Out LED’s EMULATOR CONNECTOR EXPANSION CONNECTOR (unpopulated) USB INTERFACE Figure 29. 21161 EZ-KIT Lite Audio Development System The DSP source listings ...
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APPENDIX A: Assembly Source Code Listing for 21161 EZ-KIT Lite Audio Driver (Visual DSP Project Files) 21161 EZ-KIT System Initialization Routine /*** INIT_21161_EZKIT.ASM * * ADSP-21161 EZ-KIT Initialization and Main Program Shell * Developed using the ADSP-21161 EZ-KIT LIte Evaluation ...
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Init_DSP: /* *** Enable circular buffering in MODE1 Register for revision 0.x silicon. Important when porting 2106x code!!! */ bit set MODE1 CBUFEN; /* Setup hardware interrupts, FLAG LEDs and pushbutton */ ustat2=0x00000000; /* flags 4-9 are outputs for LEDs, ...
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AD1836 Initialization Routine /*** SPORTs1&3_SPI_Emulation.ASM * * AD1836/ADSP-21161 SPI Code Register Initialization via SPI Emulation * * * * * * *********************************************************************************/ /* ADSP-21161 System Register bit definitions */ /* refer to latest DEF21161.H file for SPORT bitfield definitions */ ...
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ADC_CONTROL2 | WRITE_REG | 0x380, // read register commands ADC0_PEAK_LEVEL | READ_REG | 0x000, // status will be in rx_buf1a[13-19] memory locations ADC1_PEAK_LEVEL | READ_REG | 0x000, ADC2_PEAK_LEVEL | READ_REG | 0x000, ADC3_PEAK_LEVEL | READ_REG | 0x000, ADC_CONTROL1 ADC_CONTROL2 ADC_CONTROL3 ...
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IMASK SP1I | SP3I; SPORT_DMA_setup: r0=0x00000000; dm(SPCTL1)=r0; dm(SPCTL3)=r0; ustat1=dm(SPCTL3); ustat2=dm(SPCTL1); ustat3=dm(SP13MCTL); r0=tx_buf3a; r0=1; r0=@tx_buf3a; r0=rx_buf1a; r0=1; r0=@rx_buf1a; /* clear multichannel/miscellaneous control register for SPORT1 & SPORT3 */ R0 = 0x0; /*internally generating FS3 and *HARDWARE* loop it back ...
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NOTE: SPORT1 & SPORT3 clock and frame syncs tied together, generated by SPORT3 */ // R0 = 0x000330F1; bit set ustat2 SDEN_A | LAFS | LFS | FSR | CKRE ...
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SPORTx IOP Register Clear Init Routine /* /////////////////////////////////////////////////////////////////////////////////////// / / ROUTINE TO CLEAR AND RESET ALL SPORT1 REGISTERS / / / This routine simply clears all SPORT0/1 ctrl and DMA registers back to their / default states so that we ...
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R0; dm(MR0CCS3) = R0; /* sport1 receive multichannel companding enable registers */ R0 = 0x00000000; dm(MR1CCS0) = R0; dm(MR1CCS1) = R0; dm(MR1CCS2) = R0; dm(MR1CCS3) = R0; /* sport2 transmit multichannel companding enable registers */ R0 = 0x00000000; ...
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SPORT0 TDM Receive Interrupt Service Routine /**************************************************************************************************** / / / / Receives input data from the 2 AD1836 ADCs via SPORT1 and transmits processed audio data / back out to the 3 AD1836 Stereo DACs/Line Outputs / ***************************************************************************************************** / / ...
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Left_Channel_Out0; the*/ .GLOBAL Right_Channel_Out0; process_audio routine*/ .GLOBAL Left_Channel_Out1; .GLOBAL Right_Channel_Out1; .GLOBAL Left_Channel_Out2; .GLOBAL Right_Channel_Out2; .GLOBAL Left_Channel_AD1852; .GLOBAL Right_Channel_AD1852; .GLOBAL Left_Channel_Out_Thru; /* These serve the same function for a different set of audio */ .GLOBAL Right_Channel_Out_Thru;/* samples destined for the ...
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tx_done: r0=dm(audio_frame_timer); rti(db); r0=r0+1; dm(audio_frame_timer)=r0; /* ////////////////////////////////////////////////////////////////////////////////// */ /* get last count */ /* return from interrupt, delayed branch */ /* increment count */ /* save updated count */ ...
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APPENDIX B: C Program Source Code Listing for 21161 EZ-KIT Lite Audio Driver (Visual DSP Project Files) Main.C #include "ADDS_21161_EzKit.h" #include <def21161.h> #include <signal.h> float * DelayLine; int Index = 0; void Process_Samples( int sig_int) { Receive_Samples(); /* Perform AD1836/AD1852/SPDIF ...
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C-callable Assembly Routines for Processing Codec Data #include <asm_sprt.h> #include <def21161.h> #include "adds_21161_ezkit.h" .segment /dm seg_dmda; /* AD1836 stereo-channel data holders - used for DSP processing of audio data received from codec */ // input channels .var _Left_Channel_In0; .var _Left_Channel_In1; ...
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AD1836 */ r0 = dm(_Left_Channel_Out0 dm(_Left_Channel_Out1 dm(_Left_Channel_Out2 dm(_Left_Channel_AD1852); /* output processed right ch audio samples to AD1836 */ r0 = dm(_Right_Channel_Out0 ...
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C code for DSP System & Codec Initialization Routines #include "ADDS_21161_EzKit.h" #include <def21161.h> #include <signal.h> /**************************************************************************************************** / / / / Receives input data from the 2 AD1836 ADCs via SPORT1 and transmits processed audio data / back out to the ...
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ADC_CONTROL2 | WRITE_REG | 0x380, // read register commands ADC0_PEAK_LEVEL | READ_REG | 0x000, // status will be in rx_buf1a[13-19] memory locations ADC1_PEAK_LEVEL | READ_REG | 0x000, ADC2_PEAK_LEVEL | READ_REG | 0x000, ADC3_PEAK_LEVEL | READ_REG | 0x000, ADC_CONTROL1 | READ_REG ...
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DMASTAT) & 0xA ) asm("idle;"); interruptf( SIG_SP1I, interruptf( SIG_SP3I, SIG_IGN); *(int *) SPCTL1 = 0; *(int *) SPCTL3 = 0; return 0; } int rx0a_buf[8]; int tx2a_buf[ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}; ...
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Program_SPORT02_DMA_Channels() { xmit2a_tcb[4] = *(int *) CP2A = ((int) xmit2a_tcb + 7) & 0x3FFFF | (1<<18); rcv0a_tcb[4] = *(int *) CP0A = ((int) rcv0a_tcb } #ifdef DEBUG /* TDM audio frame/ISR counter, for debug purposes */ int audio_frame_timer = ...
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IOFLAG = FLG9|FLG8|FLG7|FLG6|FLG5|FLG4|FLG9O|FLG8O|FLG7O|FLG6O|FLG5O|FLG4O; /* flag 0-3 are inputs from pushbutton switches asm("bit clr MODE2 FLG0O | FLG1O | FLG2O | FLG3O;"); /* irqx edge sensitive asm("bit set mode2 IRQ2E | IRQ0E | IRQ1E;"); } void Blink_LED_Test( int interations ...
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C code for DSP System & Codec Initialization Routines #ifdef __ECC__ /* Insert C Definitions here.... */ int Setup_AD1836(); void Program_SPORT02_TDM_Registers(); void Program_SPORT02_DMA_Channels(); void Receive_Samples(); void Transmit_Samples(); void Init_AD1852_DACs(); void Setup_SDRAM(); void Setup_ADSP21161N(); void Blink_LED_Test( int interations ); extern float ...
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AD1836 TDM Timeslot Definitions */ #define Internal_ADC_L0 #define Internal_ADC_L1 #define AUX_ADC_L0 #define AUX_ADC_L1 #define Internal_ADC_R0 #define Internal_ADC_R1 #define AUX_ADC_R0 #define AUX_ADC_R1 #define Internal_DAC_L0 #define Internal_DAC_L1 #define Internal_DAC_L2 #define AUX_DAC_L0 #define Internal_DAC_R0 #define Internal_DAC_R1 #define Internal_DAC_R2 #define AUX_DAC_R0 /* Leave ...
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ADSP-21161 Interrupt Vector Table /* ************************************************************************************ */ /* /* /* /* For use with the 21161 EZ-KIT Lite /* /* ADI DSP Central Applications Engineering /* 10/3/00 /* ************************************************************************************ */ .EXTERN _main; .EXTERN Init_DSP; .EXTERN Count_SPORT1_RX_IRQs; .EXTERN Count_SPORT3_TX_IRQs; .EXTERN Process_AD1836_Audio_Samples; ...
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Vector address for serial port 3 primary A, secondary B RX/TX buffers (DMA Channel 6 & SP3I_svc: JUMP Count_SPORT3_TX_IRQs; RTI; RTI; // Vectors for link port DMA channels: /* 0x38 - Vector address for Link ...
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... Visual DSP Tools (21161 EZ-KIT Lite) Linker Description File ARCHITECTURE(ADSP-21161 ADSP-21161 Memory Map: // ------------------------------------------------ // Internal memory 0x0000 0000 to 0x000f ffff // ------------------------------------------------ // 0x0000 0000 to 0x0001 ffff // Block 0 0x0002 0000 to 0x0002 1fff // 0x0002 2000 to 0x0002 7fff // Block 1 0x0002 8000 to 0x0002 9fff // 0x0002 a000 to 0x0003 ffff ...
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TYPE(DM RAM) START(0x00053000) END(0x00053fff) WIDTH(32 External Memory SDRAM Mapped to Bank 0 segsdram { TYPE(DM RAM) START(0x00200000) END(0x002FFFFF) WIDTH(32 PROCESSOR p0 { LINK_AGAINST( $COMMAND_LINE_LINK_AGAINST) OUTPUT( $COMMAND_LINE_OUTPUT_FILE ) SECTIONS { // .text output section seg_rth ...
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... Analog Devices. Analog Devices Inc. reserves the right to make changes without further notice to any products here-in. Analog Devices makes no warranty, representation or guarantee regarding the suitability of its DSP and codec products for any particular purpose, nor does Analog Devices assume any liability arising out of the application or use of our DSP and codec products, and specifically disclaims any and all liability, including without limitation consequential or incidental damages ...