AN1836-AN21161 Analog Devices, AN1836-AN21161 Datasheet - Page 8

• Manufacturer Part Number: AN1836-AN21161
• Description: Interfacing the ADSP-21161 SIMD SHARC DSP to the AD1836 (24-bit/96 kHz) Multichannel Codec
• Manufacturer: Analog Devices

R. Wilson [3] and Chen [7] demonstrated that even for recursive second order IIR filter computations on a 24-bit DSP, the
noise floor of the digital filter can still go above that of the 16-bit sample and hence become audible. To compensate for this the
use of error feedback schemes or double precision arithmetic were required. So what are the implications of the fact that 24-bit
computations can introduce noise artifacts that can go above a 16-bit noise floor for complex 2
conclude when a 24-bit DSP processes 24-bit samples, that unless you take precautions a digital filter’s noise floor is always
greater than the converter's noise floor. These costly error-feedback schemes and double-precision arithmetic are unavoidable
and can add significant overhead when processing 24-bit audio data. When considering the AD1836's 24-bit data conversion
capability for a potential new audio design, the use of a native 32-bit fixed-point support becomes necessary for critical
frequency response designs to ensure that a filter algorithm’s quantization noise artifacts will not exceed the AD1836's 24-bit
105 dB input signal.
Indeed, newer 24-bit converter technology makes a strong case for 32-bit DSP processing, and such DSPs are already becoming
the processor of choice for many audio equipment manufacturers who work with 24-bit signal conversion. The ADSP-21161
SIMD architecture enables efficient coding of audio algorithms by taking advantage of two identical sets of computation units.
Each computation unit section, or processing element, gives the DSP audio engineer the ability to efficiently process complex
stereophonic algorithms concurrently by operating on left channel data in one processing element and the right channel data in
the other processing element. Single channel block processing operations such those that are used in FFT or block FIR
algorithms can be evenly distributed between both processing elements to improve algorithmic execution by as much as 80-90
% over SISD mode when 1 computation unit is enabled. In addition, the ADSP-21161 includes desirable peripheral
enhancements to perform real-time audio computations, including:
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Native 32-bit fixed and 32-/40 bit floating point support. With the use of 32-bit filter coefficients, giving precise
placement of poles and zeros while ensuring that the digital filters noise floor remains below that of the ADC/DAC.
Fast and flexible arithmetic with the use of a 2 DSP computation cores, which are also called Processing Elements. Each
Processing Element (PEX and PEY) consists of an ALU, multiplier, shifter and register file. These dual PEs provide more
computational horse power to execute the basic building blocks of audio algorithms; such as FIR filters, IIR filters, and
FFT processing.
Extended dynamic range for extended sum-of-product calculations with four 80-bit fixed-point accumulators
Single-cycle fetch of four operands for two sum-of-products calculations in SIMD mode.
Hardware circular buffer support for up to 32 concurrent audio delay-lines (16 primary, 16 alternate), which is beneficial
for certain audio applications requiring the use of a large number of delay-line pointers
Efficient looping and branching for repetitive DSP operations through an optimized Program Sequencer
1 Megabit on-chip SRAM, and an on-chip SDRAM controller providing low-cost bulk storage for code and lengthy delay
lines for time-delay effects and digital filters
Integrated glueless multiprocessing support for large signal processing systems such as 64 channel mixers
4 SPORTs with I
enhancement and data path programmability of the serial data pins allows the designer to configure the SPORTs for 16 I2S
transmit channels, or 16 I2S receive channels, or a combination of 12 transmit/8 receive, 8 transmit- 8 receive, or 4
transmit- 8 receive I
variety of ADCs, DACs, SP/DIF or AES/transmitter and receivers used in a variety of pro and consumer audio
applications.
2
S support, providing two data pins, which can be programmable as transmitters or receivers. The I
2
S channels. I
2
S is an industry-wide standard which provides a glueless interconnection to a wide
nd
- order filters? We can
2
S