AN1836-AN21161 Analog Devices, AN1836-AN21161 Datasheet - Page 48

• Manufacturer Part Number: AN1836-AN21161
• Description: Interfacing the ADSP-21161 SIMD SHARC DSP to the AD1836 (24-bit/96 kHz) Multichannel Codec
• Manufacturer: Analog Devices

.var rx_buf1a[21];
/* ISR counters, for debug purposes to see how many times SPORT DMA interrupts are serviced */
.VAR
.VAR
.section /pm pm_code;
/////////////////////////////////////////////////////////////////////////////////////////
//
//
//
/////////////////////////////////////////////////////////////////////////////////////////
Program_AD1836_regs_via_SPI:
powerdown_reset_AD1836:
powerdwm_not_done_yet:
Wait_Approx_1s:
waitloop:
Program SPORT1 & SPORT3 Control Registers for SPI emulation control
ADC_CONTROL2 | WRITE_REG | 0x380,
// read register commands
ADC0_PEAK_LEVEL | READ_REG | 0x000, // status will be in rx_buf1a[13-19] memory locations
ADC1_PEAK_LEVEL | READ_REG | 0x000,
ADC2_PEAK_LEVEL | READ_REG | 0x000,
ADC3_PEAK_LEVEL | READ_REG | 0x000,
ADC_CONTROL1
ADC_CONTROL2
ADC_CONTROL3
SP1I_counter = 0;
SP3I_counter = 0;
r0=0x00000000;
dm(SPCTL1)=r0;
dm(SPCTL3)=r0;
ustat1=dm(SPCTL3);
ustat2=dm(SPCTL1);
ustat3=dm(SP13MCTL);
r0=powerdown_AD1836;
r0=1;
r0=@powerdown_AD1836; dm(C3A)=r0;
r0=powerdown_rx_buf0a; dm(II1A)=r0;
r0=1;
r0=@powerdown_rx_buf0a; dm(C1A)=r0;
/* clear multichannel/miscellaneous control register for SPORT1 & SPORT3 */
R0 = 0x0;
R0 = 0x0011002B;
R0 = 0;
bit set ustat1 DDIR | SDEN_A | LAFS | LFS |
dm(SPCTL3) = ustat1;
bit set ustat2 SDEN_A | LAFS | LFS | FSR | CKRE | SLEN16 | SPEN_A;
bit clr ustat2 DDIR | IFS | ICLK;
dm(SPCTL1) = ustat2;
bit set imask SP1I | SP3I;
idle;
R1 = 0x00000008;
R0 = DM(DMASTAT);
R0 = R0 AND R1;
IF NE jump powerdwm_not_done_yet;
bit clr imask SP1I|SP3I;
lcntr = 3000, do waitloop until lce;
bit clr ustat1 0xFFFFFFFF;
dm(SPCTL1) = ustat1;
dm(SPCTL3) = ustat1;
IRPTL=0;
nop;
| READ_REG | 0x000,
| READ_REG | 0x000,
| READ_REG | 0x000;
nop;
nop;
nop;
dm(II3A)=r0;
dm(IM3A)=r0;
dm(IM1A)=r0;
dm(SP13MCTL) = R0;
dm(DIV3) = R0;
dm(DIV1) = R0;
// initially clear SPORT control register
/* Internal DMA6 memory address */
/* Internal DMA6 memory access modifier
/* Contains number of DMA6 transfers to be done */
/* Internal DMA2 memory address
/* Internal DMA2 memory access modifier
/* Contains number of DMA2 transfers to be done */
// enable SPORT1 RX and SPORT3 TX interrupts
// Test for SPORT3
// disable SPORT1 RX and SPORT3 TX interrupts
IFS | FSR | CKRE | ICLK | SLEN16 | SPEN_A;
//
//
//
*/
*/
*/