AN1836-AN21161 Analog Devices, AN1836-AN21161 Datasheet - Page 36

• Manufacturer Part Number: AN1836-AN21161
• Description: Interfacing the ADSP-21161 SIMD SHARC DSP to the AD1836 (24-bit/96 kHz) Multichannel Codec
• Manufacturer: Analog Devices

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5.2 Readback Of AD1836 Registers For Verification And Debugging Using A Zero-
Overhead DO LOOP
There are times over the debugging stage of driver code the DSP programmer may want to verify the desired values of the
AD1836's internal registers. One easy way to do this is to set up an output buffer where all read requests of registers can be
stored after codec initialization. The readback and status of codec registers can also be done using a hardware loop. The
following assembly language instructions shown below are used to initiate codec read requests of registers shown in the
Init_Codec_Registers[ ] buffer. The results of the read requests are then placed in an output buffer called
Codec_Init_Results[. On the 2116 EZ-KIT Lite, the AD1836 registers can then be verified with JTAG emulator or the VDSP
USB/JTAG debugger by setting a breakpoint after this section of code and opening up the memory window that shows the
values stored in the memory buffer. After successful debugging of custom code these instructions can then be removed.
/* Verify integrity of AD1836 register states to see if communication was successful */
verify_reg_writes:
///////////////////////////
// SPORT1/3 version
///////////////////////////
ad1836_register_status: nop;
___________________________________________
///////////////////////////
// SPI version
///////////////////////////
ad1836_register_status: nop;
Explanation Of The AD1836 Codec Register Readback Loop :
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The IDLE instruction will tell the DSP to do nothing but wait for a SPORT3/SPI transmit interrupt after data has be written
the the SPORT/SPI transmit buffer. Waiting for the SPORT/SPI interrupt will guarantee that all data in the transmit buffer
has been shifted out on the serial bus, thus telling us it is safe to go the next codec register data value in the initialization
buffer and place the word in the 'transmit buffer' queue.
The buffer pointers I4 and I5 is first set to point to the top of the codec register buffer and codec results buffer.
The Loop Counter Register LCNTR is set to the number of registers to be read from the AD1836.
Memory writes from TX3A or SPITX will set a read request for the codec register address specified in the
Init_Codec_Registers[ ] buffer.
One IDLE instruction is required to correctly readback the codec after we transmit the request.
The pointer I5 copies the register address and data in the Codec_Init_Results[ ] buffer for every read request.
I7 = Init_Codec_Registers;
M7 = 1;
I5 = Codec_Init_Results;
LCNTR = 15, Do ad1836_register_status UNTIL LCE;
lcntr = 15, DO Set_1836_Regs until LCE;
r13 = dm(I7,M7);
DM(TX3A) = r13;
idle;
r3 = dm(RX1A);
dm(I5,1) = r3;
r13 = dm(I7,M7);
DM(SPITX) = r13;
idle;
r3 = dm(SPIRX);
dm(I5,1) = r3;
/* fetch value of requested indexed register data */
/* store to results buffer */
/* fetch value of requested indexed register data */
/* store to results buffer */