AN1836-AN21161 Analog Devices, AN1836-AN21161 Datasheet - Page 47

• Manufacturer Part Number: AN1836-AN21161
• Description: Interfacing the ADSP-21161 SIMD SHARC DSP to the AD1836 (24-bit/96 kHz) Multichannel Codec
• Manufacturer: Analog Devices

AD1836 Initialization Routine
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/* ADSP-21161 System Register bit definitions */
/*
#include
.GLOBAL
.GLOBAL
.GLOBAL
//.EXTERN
.GLOBAL
.GLOBAL
// AD1836 codec SPI control/status register definitions
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
.section/dm dm_data;
/* Powerdown ADCs and DACs twice to get around AD1836 SPI/powerdown anomaly */
.var powerdown_AD1836[4] =
.var powerdown_rx_buf0a[4]; // rx dma dummy buffer not used for anything;
//
//
//
//
//
.var tx_buf3a[21] = //program register commands
anomaly
refer to latest DEF21161.H file for SPORT bitfield definitions */
SPORTs1&3_SPI_Emulation.ASM
AD1836 codec register commands - Serial SPI 16-bit Word Format as follows:
AD1836/ADSP-21161 SPI Code Register Initialization via SPI Emulation
"def21161.h"
Program_AD1836_regs_via_SPI;
Count_SPORT1_RX_IRQs;
Count_SPORT3_TX_IRQs;
Wait_Approx_999us;
Wait_Approx_1500ms;
Wait_Approx_167ms;
READ_REG
WRITE_REG
DAC_CONTROL1
DAC_CONTROL2
DAC_VOLUME0
DAC_VOLUME1
DAC_VOLUME2
DAC_VOLUME3
DAC_VOLUME4
DAC_VOLUME5
ADC0_PEAK_LEVEL
ADC1_PEAK_LEVEL
ADC2_PEAK_LEVEL
ADC3_PEAK_LEVEL
ADC_CONTROL1
ADC_CONTROL2
ADC_CONTROL3
RESERVED_REG
DAC_CONTROL1 | WRITE_REG | 0x000,
DAC_CONTROL1 | WRITE_REG | 0x000,
DAC_CONTROL2 | WRITE_REG | 0x000,
DAC_VOLUME0
DAC_VOLUME1
DAC_VOLUME2
DAC_VOLUME3
DAC_VOLUME4
DAC_VOLUME5
ADC_CONTROL1 | WRITE_REG | 0x000,
ADC_CONTROL1 | WRITE_REG | 0x000,
ADC_CONTROL3 | WRITE_REG | 0x000,
ADC_CONTROL2 | WRITE_REG | 0x380,
D15 to D12
D11
D10
D9 to D0
| WRITE_REG | 0x3FF,
| WRITE_REG | 0x3FF,
| WRITE_REG | 0x3FF,
| WRITE_REG | 0x3FF,
| WRITE_REG | 0x3FF,
| WRITE_REG | 0x3FF,
DAC_CONTROL1 | WRITE_REG | 0x004,
DAC_CONTROL1 | WRITE_REG | 0x004,
ADC_CONTROL1 | WRITE_REG | 0x080,
ADC_CONTROL1 | WRITE_REG | 0x080;
********************************************
0x0800
0x0000
0x0000
0x1000
0x2000
0x3000
0x4000
0x5000
0x6000
0x7000
0x8000
0x9000
0xA000
0xB000
0xC000
0xD000
0xE000
0xF000
= Codec Register Address
= Read/Write register (1=rd, 0=wr)
= reserved bit, clear to zero
= Data Field for codec register
// we "OR" in address, rd/wr, and register data
// for ease in reading register values
// write DAC_CTL1 twice to workaround pwdwn SPI anomaly
John Tomarakos
ADI DSP Applications Group
Revision 2.0
03/05/01
// write ADC_CTL1 twice to workaround pwdwn SPI
// 256*Fs Clock Mode !!!, differential PGA mode
// SOUT MODE = 110 --> TDM Mode, Master device
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