AN1836-AN21161 Analog Devices, AN1836-AN21161 Datasheet - Page 29
![no-image](/images/manufacturer_photos/0/0/56/analog_devices_sml.jpg)
AN1836-AN21161
Manufacturer Part Number
AN1836-AN21161
Description
Interfacing the ADSP-21161 SIMD SHARC DSP to the AD1836 (24-bit/96 kHz) Multichannel Codec
Manufacturer
Analog Devices
Datasheet
1.AN1836-AN21161.pdf
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4. Programming the AD1836's Slave SPI Port
The AD1836 has an SPI compatible slave control port, which is a four wire serial control port. The format is similar to the
Motorola SPI format. This allows the following SPI slave register access options:
The maximum serial bit clock frequency supported via the AD1836 slave SPI port is 8 MHz.
There are two approaches supported on the ADSP-21161 EZ-KIT Lite for programming the AD1836 registers. One is using
the ADSP-21161's Serial Peripheral Interface (compatible) port. Another method is currently required is to use "SPI
Emulation" using SPORT1 and SPORT3 on the ADSP-21161. This is needed to work around an AD1836 anomaly where the
AD1836's CCLK pin needs to be run in continuous mode to work around the AD1836's "extra 17
SPI protocol uses a gated serial clock, it is difficult to provide the extra clock in order to latch the data, since this is not possible
with SPI (In SPI, the serial clock is gated and goes high after the device select is disabled).
The 21161's EZ-KIT Lite supports both methods for programming the AD1836 registers. Jumper JP23 connects th4e AD1836
pins to either the SPI port or the SPORT1/SPORT3 pair. With JP23 on, the ADSP-21161's SPORT1 and SPORT3 are
interfaced toe the AD1836 SPI port. Removing the jumper connects the ADSP-21161's SPI port to the AD1836's slave SPI
port. The block diagrams detailing both approaches are shown below:
1.
2.
3.
Figure 23. AD1836 Port connected to SPORT1/SPORT3 (JP23 jumper installed)
Programming the internal control registers for the ADCs and DACs
Allows reading of ADC peak signal levels through the peak detectors
The DAC output levels may be independently programmed by means of an internal attenuator adjustable in 1024 linear
steps.
Figure 22. AD1836 Port connected to the SPI port (JP23 removed)
AD1836
Control
AD1836
Port
Control
SPI
Port
SPI
CLATCH
CDATA
CLATCH
CCLK
COUT
CDATA
CCLK
COUT
SCLK3
SCLK1
FS3
FS1
D3A
D1A
SPICLK
FLAG0
MOSI
MISO
ADSP-
21161
ADSP-
21161
th
CCLK" anomaly. Since the
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