AN1836-AN21161 Analog Devices, AN1836-AN21161 Datasheet - Page 14

• Manufacturer Part Number: AN1836-AN21161
• Description: Interfacing the ADSP-21161 SIMD SHARC DSP to the AD1836 (24-bit/96 kHz) Multichannel Codec
• Manufacturer: Analog Devices

A new audio output frame begins with a low to high transition of FSTDM. FSTDM is synchronous to the rising edge of
ABCLK. On the immediately following falling edge of ABCLK, the ADSP-21161 samples the assertion of FSTDM. This
falling edge marks the time when both sides the TDM link are aware of the start of a new audio frame. On the next rising of
ABCLK, the ADSP-21161 transitions DSDATA1 into the first bit position of slot 0 (MSB). Each new bit position is presented
to the TDM link on a rising edge of ABCLK, and subsequently sampled by AD1836 on the following falling edge of ABCLK.
This sequence ensures that data transitions, and subsequent sample points for both incoming and outgoing data streams are time
aligned.
D2A/DSDATA’s composite stream is MSB justified (MSB first) with all non-valid slots’ bit positions stuffed with 0’s by the
ADSP-21161. The DSP software initializes the transmit DMA buffer to 0s in the AD1836 driver. (shown in Appendix A).
The 24-bit audio data contained within the 32-bit timeslot is left justified, i.e., the 24-bit information processed by the AD1836
DACs reside in bit positions 31 to 8.
In the event that there are less than 32-valid bits within an assigned and valid time slot, the ADSP-21161 always stuff all trailing
non-valid bit positions of the 32-bit slot with 0’s.
When mono audio sample streams are output from the ADSP-21161, the programmer can optionally ensure that each left and
right sample stream pair time slots be filled with the same data.
2.2 AD1836/ADSP-21161 Audio Input Frame (SDATA_IN to DR0)
The audio input frame data streams correspond to the multiplexed bundles of all digital input data targeting the ADSP-21161.
As is the case for audio output frame, each AD1836 audio input frame consists of 8, 32-bit time slots. The following diagram
illustrates the time slot based AD1836 TDM protocol:
ABCLK (SCLK0)
ASDATA1 (D0A)
FSTDM (FS0)
End of previous
Audio Frame
Figure 14. AD1836 TDM Audio Input Frame - AD1836 to ADSP-21161
Start of new
Audio Frame
31
12.288
MHz
30
29
DSDATA1
Figure 13. Start of an Audio Output Frame
81.4 nS
ABCLK
FSTDM
Slot 0
3
End of previous
Audio Frame
2
1
AD1836 generates frame sync assertion here
D31
0
first DSDATA1 bit of
ADSP-21161 drives
31
D30
Slot 1
frame here
D29
0
(48 KHz)
20.8uS
31
Slot 2
FS0
D2A
SCLK2
0
31
Slot 3
0
31
Slot 7
0