AN1836-AN21161 Analog Devices, AN1836-AN21161 Datasheet - Page 23

• Manufacturer Part Number: AN1836-AN21161
• Description: Interfacing the ADSP-21161 SIMD SHARC DSP to the AD1836 (24-bit/96 kHz) Multichannel Codec
• Manufacturer: Analog Devices

3.5 SPORT DMA Registers For The ADSP-21161
The following register descriptions are provided in the defs21161.h file for programming the DMA registers associated with the
I/O processor’s DMA controller. We will next examine how these registers are programmed for DMA chaining, in which the
DMA registers are reinitialized automatically whenever a serial port interrupt request is generated. [Registers used in the EZ-
KIT driver are highlighted in BLUE]
SPORT0 RX/TX
Channel A
SPORT0 RX/TX
Channel B
SPORT1 RX/TX
Channel A
SPORT1 RX/TX
Channel B
SPORT2 RX/TX
Channel A
SPORT2 RX/TX
Channel B
SPORT3 RX/TX
Channel A
SPORT3 RX/TX
Channel B
DMA Register Description
DMA Channel 0 Index Register
DMA Channel 0 Modify Register
DMA Channel 0 Count Register
DMA Channel 0 Chain Pointer Register
DMA Channel 0 General Purpose Register GP0A
DMA Channel 1 Index Register
DMA Channel 1 Modify Register
DMA Channel 1 Count Register
DMA Channel 1 Chain Pointer Register
DMA Channel 1 General Purpose Register GP0B
DMA Channel 2 Index Register
DMA Channel 2 Modify Register
DMA Channel 2 Count Register
DMA Channel 2 Chain Pointer Register
DMA Channel 2 General Purpose Register GP1A
DMA Channel 3 Index Register
DMA Channel 3 Modify Register
DMA Channel 3 Count Register
DMA Channel 3 Chain Pointer Register
DMA Channel 3 General Purpose Register GP1B
DMA Channel 4 Index Register
DMA Channel 4 Modify Register
DMA Channel 4 Count Register
DMA Channel 4 Chain Pointer Register
DMA Channel 4 General Purpose Register GP2A
DMA Channel 5 Index Register
DMA Channel 5 Modify Register
DMA Channel 5 Count Register
DMA Channel 5 Chain Pointer Register
DMA Channel 5 General Purpose Register GP2B
DMA Channel 6 Index Register
DMA Channel 6 Modify Register
DMA Channel 6 Count Register
DMA Channel 6 Chain Pointer Register
DMA Channel 6 General Purpose Register GP3A
DMA Channel 7 Index Register
DMA Channel 7 Modify Register
DMA Channel 7 Count Register
DMA Channel 7 Chain Pointer Register
DMA Channel 7 General Purpose Register GP3B
Table 6. SPORT DMA IOP Registers
DMA Register IOP Address
II0A
IM0A
C0A
CP0A
II0B
IM0B
C0B
CP0B
II1A
IM1A
C1A
CP1A
II1B
IM1B
C1B
CP1B
II2A
IM2A
C2A
CP2A
II2B
IM2B
C2B
CP2B
II3A
IM3A
C3A
CP3A
II3B
IM3B
C3B
CP3B
0x60
0x61
0x62
0x63
0x64
0x80
0x81
0x82
0x83
0x84
0x68
0x69
0x6A
0x6B
0x6C
0x88
0x89
0x8A
0x8B
0x8C
0x70
0x71
0x72
0x73
0x74
0x90
0x91
0x92
0x93
0x94
0x78
0x79
0x7A
0x7B
0x7C
0x98
0x99
0x9A
0x9B
0x9C