AN1836-AN21161 Analog Devices, AN1836-AN21161 Datasheet - Page 20

• Manufacturer Part Number: AN1836-AN21161
• Description: Interfacing the ADSP-21161 SIMD SHARC DSP to the AD1836 (24-bit/96 kHz) Multichannel Codec
• Manufacturer: Analog Devices

3.3 Serial Port Related IOP Registers
This section briefly highlights the list of available SPORT-related IOP registers that are required to be programmed when
configuring the SPORTs for Multichannel Mode on the 21161 EZ-KIT lite in order to communicate with the AD1836 via
SPORT0 and SPORT2. To program these registers, you write to the appropriate address in memory using the symbolic macro
definitions supplied in the def21161.h file (included with the Visual DSP tools in the /INCLUDE/ directory). External
devices such as another ADSP-21161, or a host processor, can write and read the SPORT control registers to set up a serial port
DMA operation or to enable a particular SPORT. These registers are listed in Table 5 below. The SPORT DMA IOP registers
are covered in section 4.8. As we will see in the next section, many of the available registers shown below need to be
programmed to set up Multichannel Mode. These registers are highlighted in bold text.
SPORT0
SPORT2
Within the 4 SPORTs on the ADSP-21161, there are 16 SPORT data buffers associated with the 16 serial data pins. In
Multichannel Mode, the available SPORT data buffers are active are the channel A registers (which are highlighted below)
only. It is these registers that are actually used to transfer data between the AD1836 and the DMA controller on the ADSP-
21161. The DMA controller is used to transfer data to and from internal memory without any intervention from the core.
SPORT
Data
Buffers
Table 5. Serial Port IOP Registers for SPORT0/SPORT2 MCM Pairing
Register
SPCTL0
DIV0
MR0CS0
MR0CS1
MR0CS2
MR0CS3
MR0CCS0
MR0CCS1
MR0CCS2
MR0CCS3
SPCTL2
DIV2
MT2CS0
MT2CS1
MT2CS2
MT0CS3
MT2CCS0
MT2CCS1
MT2CCS2
MT2CCS3
SP02MCTL
TX0A
TX0B
RX0A
RX0B
TX2A
TX2B
RX2A
RX2B
0x1D8
0x1DA
0x1DC
0x1DE
IOP Address
0x1C0
0x1C5
0x1C7
0x1C9
0x1CB
0x1CD
0x1C8
0x1CA
0x1CC
0x1CE
0x1D0
0x1D5
0x1D7
0x1D9
0x1DB
0x1DD
0x1DF
0x1C1
0x1C2
0x1C3
0x1C4
0x1D1
0x1D2
0x1D3
0x1D4
Description
SPORT0 control register
SPORT0 clock and frame sync divisor
SPORT0 multichannel receive select 0 (channels 31-0)
SPORT0 multichannel receive select 1 (channels 63-32)
SPORT0 multichannel receive select 2 (channels 95-64)
SPORT0 multichannel receive select 3 (channels 127-96)
SPORT0 multichannel receive compand select 0 (channels 31-0)
SPORT0 multichannel receive compand select 1 (channels 63-32)
SPORT0 multichannel receive compand select 2 (channels 95-64)
SPORT0 multichannel receive compand select 3 (channels 127-96)
SPORT2 control register
SPORT2 clock and frame sync divisor
SPORT2 multichannel transmit select 0 (channels 31-0)
SPORT2 multichannel transmit select 1 (channels 63-32)
SPORT2 multichannel transmit select 2 (channels 95-64)
SPORT2 multichannel transmit select 3 (channels 127-96)
SPORT2 multichannel transmit compand select 0 (channels 31-0)
SPORT2 multichannel transmit compand select 1 (channels 63-32)
SPORT2 multichannel transmit compand select 2 (channels 95-64)
SPORT2 multichannel transmit compand select 3 (channels 127-96)
SPORT 0/2 Multichannel Control Register
SPORT0 transmit data buffer, channel A data
SPORT0 transmit data buffer, channel B data
SPORT0 receive data buffer, channel A data
SPORT0 receive data buffer, channel B data
SPORT2 transmit data buffer, channel A data
SPORT2 transmit data buffer, channel B data
SPORT2 recieve data buffer, channel A data
SPORT2 receive data buffer, channel B data