AN1836-AN21161 Analog Devices, AN1836-AN21161 Datasheet - Page 38

• Manufacturer Part Number: AN1836-AN21161
• Description: Interfacing the ADSP-21161 SIMD SHARC DSP to the AD1836 (24-bit/96 kHz) Multichannel Codec
• Manufacturer: Analog Devices

copied from the output queue into the transmit DMA buffer, where it is then transferred to the SPORT transmit data register for
shifting out of the serial port. The AD1836 codec processing instructions can be executed with either the transmit or receive
interrupt.
Fig 27. SPORT 0 RX Interrupt Service Routine Data Flow Structure for AD1836 Audio Processing
SPORT0 RX Interrupt Service Routine Workflow
1) Get new audio samples received from AD1836 via the SPORT receive DMA buffer rx_buf0a[ ] .
2) Save new audio samples to Audio Variables in Memory for DSP Processing
6) Run Desired DSP Algorithm
4) Retrieve processed audio samples from Audio Variables in Memory
7) Copy DSP Algorithm Results to AD1836 DACs via the SPORT DMA buffer tx_buf2a[ ] .
SPORT0 TDM (ADC) Data
SPORT2 TDM (DAC)Data
RX0A register
TX2A register
DMA transfer
transfer to
Memory
Internal
Memory
Internal
DMA
from
RX0A DMA Interrupt Generated
when RX_BUF0a fills up with new
AD1836 audio samples. The data is
quickly saved to variables in memory
for audio processing
rx_buf0a + Internal_ADC_L0
tx_buf2a+ Internal_DAC_L0
.VAR RX_BUF0a [8]
.VAR TX_BUF2a [8]
+ Internal_ADC_R0
+ AUX_ADC_L0
+ Internal_ADC_L1
+ Internal_DAC_L1
+ AUX_DAC_L0
+ Internal_DAC_R0
+ Internal_DAC_R1
+ Internal_DAC_R2
+ AUX_DAC_R0
RX0A DMA Buffer
+ Internal_ADC_L0
+ AUX_ADC_R0
TX2A DMA Buffer
+ Internal_DAC_L2
DM Memory Variables(.VARs)
Left_Channel_In0
Left_Channel_In1
Left_Channel_SPDIF_rx
Right_Channel_In0
Right_Channel_In1
Right_Channel_SPDIF_rx
Left_Channel_Out0
Left_Channel_Out1
Left_Channel_Out2
Left_Channel_AD1852
Right_Channel_Out0
Right_Channel_AD1852
Right_Channel_Out1
Right_Channel_Out2
SPORT0 RX ISR Flow
DSP Audio
Algorithm
Routines