AN1836-AN21161 Analog Devices, AN1836-AN21161 Datasheet - Page 61
![no-image](/images/manufacturer_photos/0/0/56/analog_devices_sml.jpg)
AN1836-AN21161
Manufacturer Part Number
AN1836-AN21161
Description
Interfacing the ADSP-21161 SIMD SHARC DSP to the AD1836 (24-bit/96 kHz) Multichannel Codec
Manufacturer
Analog Devices
Datasheet
1.AN1836-AN21161.pdf
(70 pages)
- Current page: 61 of 70
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}
int
int
/* TCB = "Transfer Control Block" */
/* TCB format: ECx (length of destination buffer),
int
int
void
{
}
while ( (*(int*) DMASTAT) & 0xA )
interruptf(
interruptf( SIG_SP3I, SIG_IGN);
*(int *) SPCTL1 = 0;
*(int *) SPCTL3 = 0;
return 0;
rx0a_buf[8];
tx2a_buf[8] = { 0x00000000,
rcv0a_tcb[8]
xmit2a_tcb[8] = {0, 0, 0, 0, 0, 8, 1, (int) tx2a_buf};
Program_SPORT02_TDM_Registers()
*(int *) DIV0 = 0;
*(int *) DIV2 = 0;
/* SPORT0 and SPORT2 are being operated in "multichannel" mode.
This is synonymous with TDM mode which is the operating mode for the AD1836 */
/* SPORT 0&2
/* SP02MCTL = 0x000000E2,
/* Multichannel Frame Delay=1, Number of Channels = 8, LB disabled */
*(int *) SP02MCTL = NCH_8 | MFD1;
/* sport0 control register set up as a receiver in MCM */
/* sport 0 control register SPCTL0 = 0x000C01F0 */
*(int *) SPCTL0 =
/* sport2 control register set up as a transmitter in MCM */
/* sport 2 control register, SPCTL2 = 0x000C01F0 */
*(int *) SPCTL2 =
/* sport0 & sport2 receive and transmit multichannel word enable registers */
/* enable receive channels 0-7 */
/* enable transmit channels 0-7 */
*(int *) MR0CS0 = *(int *) MT2CS0 =0x000000FF;
/* sport0 & sport2 receive & transmit multichannel companding enable registers */
/* no companding for our 8 active timeslots*/
/* no companding on SPORT0 receive */
/* no companding on SPORT2 transmit */
*(int *) MR0CCS0 = *(int *) MT2CCS0 = 0;
asm("idle;");
EMx (destination buffer step size),
EIx (destination buffer index (initialized to start address)),
GPx ("general purpose"),
CPx ("Chain Point register"; points to last address (IIx) of
Cx
IMx (source buffer step size),
IIx (source buffer index (initialized to start address))
(length of source buffer),
= {0, 0, 0, 0, 0, 8, 1, (int) rx0a_buf};
Miscellaneous Control Bits Registers */
SIG_SP1I,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000};
SCHEN_A | SDEN_A | SLEN32;
SCHEN_A | SDEN_A | SLEN32;
Hold off on MCM enable, and number of TDM slots to 8 active channels */
SIG_IGN);
/* receive buffer (DMA)*/
/* transmit buffer (DMA)*/
next TCB to jump to
upon completion of this TCB.),
/* SPORT2 transmit tcb */
/* SPORT0 receive tcb */
*/
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