AN1836-AN21161 Analog Devices, AN1836-AN21161 Datasheet - Page 21

• Manufacturer Part Number: AN1836-AN21161
• Description: Interfacing the ADSP-21161 SIMD SHARC DSP to the AD1836 (24-bit/96 kHz) Multichannel Codec
• Manufacturer: Analog Devices

3.4 SPORT0/SPORT2 IOP Register Configurations For Audio Processing At 48 kHz
The configuration for SPORT0 and SPORT2, for use with the ADSP-21161 EZ-KIT Lite at a fixed 48 kHz sample rate, is set
up as follows:
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Program_SPORT02_TDM_Registers:
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32-bit serial word length
Enable SPORT0 receive A channel DMA functionality
Enable SPORT2 transmit A channel DMA functionality
Enable DMA chaining functionality for SPORT0 receive A channel and SPORT2 transmit A channel
External Serial Clock (SCLK0) - the codec provides the serial clock to the ADSP-21161.
Transmit and Receive DMA chaining enabled. The DSP program declares 2 buffers - rx_buf0a[8] and tx_buf2a[0] - for
DMA transfers of SPORT0/2 receive and transmit serial data. Both buffers reserve 8 locations in memory to reflect the
AD1836 time slot allocation for the codec. DMA chaining is almost certainly required (and strongly recommended), or the
interrupt service overhead will chew up too more of the DSP’s bandwidth.
Multichannel Frame Delay = 1, i.e., the frame sync occurs 1 SCLK cycle before MSB of 1
TDM frame. New frames are marked by a HI pulse driven out on FSTDM one serial clock period before the frame begins.
The ADSP-21161 shifts it's data based on an externally generated 48 kHz frame sync (FS0). It is actually a 48 kHz frame
rate since the AD1836 TDM sample rate operates at 48 kHz (NOTE: 96 kHz in TDM mode is not supported). Since the
AD1836 serial clock is 12.288 MHz, a divide factor or 256 (256xFs) will produce a 48 kHz internally generated frame
sync.
No companding.
/* SPORT0 and SPORT2 are being operated in "multichannel" mode.
This is synonymous with TDM mode which is the operating mode for the AD1836 */
/* SPORT 0&2
R0
dm
/* sport0 control register set up as a receiver in MCM */
R0
dm
/* sport2 control register set up as a transmitter in MCM */
R0
dm
/* sport 0 & 2 frame sync divide registers */
/* External Clock and Frame Sync generated by AD1836 */
R0
dm(DIV0) = R0;
dm(DIV2) = R0;
/*sport0 & sport2 receive & transmit multichannel companding enable registers*/
R0
dm(MR0CCS0) = R0;
dm(MR0CCS1) = R0;
dm(MR0CCS2) = R0;
dm(MR0CCS3) = R0;
(SP02MCTL) =
(SPCTL0) =
(SPCTL2) =
= NCH_8 | MFD1; /*Hold off on MCM enable, and no of TDM slots to 8 active channels*/
= SCHEN_A | SDEN_A | SLEN32;
= SCHEN_A | SDEN_A | SLEN32;
= 0x00000000;
= 0x00000000;
R0
R0
Miscellaneous Control Bits Registers */
R0
;
;
; /*Multichannel Frame Delay=1, Number of Channels = 8, LB disabled*/
/* sport 0 control register SPCTL0 = 0x000C01F0 */
/* sport 2 control register, SPCTL2 = 0x000C01F0 */
/* no companding for our 8 active timeslots*/
/* no companding on SPORT0 receive */
st
word/timeslot in the audio