AN1836-AN21161 Analog Devices, AN1836-AN21161 Datasheet - Page 53

• Manufacturer Part Number: AN1836-AN21161
• Description: Interfacing the ADSP-21161 SIMD SHARC DSP to the AD1836 (24-bit/96 kHz) Multichannel Codec
• Manufacturer: Analog Devices

SPORT0 TDM Receive Interrupt Service Routine
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/* ADSP-21161 System Register bit definitions */
#include
/* AD1836 TDM Timeslot Definitions */
/* 8 successive 32 bit samples (representing 8 channels of audio data) make up the 256 bit TDM frame */
#define
#define
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rx0a_buf[8] - DSP SPORT recieve buffer
Slot # Description
------ --------------------------------------
0
1
2
3
4
5
6
7
tx2a_buf[8] - DSP SPORT transmit buffer
Slot # Description
------ --------------------------------------
0
1
2
3
4
5
6
7
This Serial Port 0 Recieve Interrupt Service Routine performs arithmetic computations on
the SPORT1 receive DMA buffer (rx_buf) and places results to SPORT1 transmit DMA buffer (tx_buf)/
Receives input data from the 2 AD1836 ADCs via SPORT1 and transmits processed audio data
back out to the 3 AD1836 Stereo DACs/Line Outputs
Internal ADC 0 Left Channel
Internal ADC 1 Left Channel
External Auxilliary ADC 0 Left Chan.
External Auxilliary ADC 1 Left Chan.
Internal ADC 1 Right Channel
Internal ADC 1 Right Channel
External Auxilliary ADC 0 Right Chan.
External Auxilliary ADC 1 Right Chan.
Internal DAC 0 Left Channel
Internal DAC 1 Left Channel
Internal DAC 2 Left Channel
External Auxilliary DAC 0 Left Chan.
Internal DAC 0 Right Channel
Internal DAC 1 Right Channel
Internal DAC 2 Left Channel
External Auxilliary DAC 0 Right Chan.
"def21161.h"
Internal_ADC_L0
Internal_ADC_L1
AUX_ADC_L0
AUX_ADC_L1
Internal_ADC_R0
Internal_ADC_R1
AUX_ADC_R0
AUX_ADC_R1
Internal_DAC_L0
Internal_DAC_L1
Internal_DAC_L2
AUX_DAC_L0
Internal_DAC_R0
Internal_DAC_R1
Internal_DAC_R2
AUX_DAC_R0
Process_AD1836_Audio_Samples; /* Label of code listed here to get samples into and out of*/
Left_Channel_In0;
Right_Channel_In0; /* Process_AD1836_Audio_Samples routine to the process_audio routine*/
Left_Channel_In1;
Right_Channel_In1;
Left_Channel_SPDIF_rx;
Right_Channel_SPDIF_rx;
AD1836 - SPORT0 RX INTERRUPT SERVICE ROUTINE
/* These will tranfer ADC samples of interest from the*/
/* SPORT DMA buffers and process_audio routine*/
DSP Data Memory Address
-----------------------------------------------
DM(rx0a_buf + 0) = DM(rx0a_buf + Internal_ADC_L0) /
DM(rx0a_buf + 1) = DM(rx0a_buf + Internal_ADC_L1) /
DM(rx0a_buf + 2) = DM(rx0a_buf + AUX_ADC_L0)
DM(rx0a_buf + 3) = DM(rx0a_buf + AUX_ADC_L1)
DM(rx0a_buf + 4) = DM(rx0a_buf + Internal_ADC_R0) /
DM(rx0a_buf + 5) = DM(rx0a_buf + Internal_ADC_R1) /
DM(rx0a_buf + 6) = DM(rx0a_buf + AUX_DAC_R0)
DM(rx0a_buf + 7) = DM(rx0a_buf + AUX_DAC_R1)
DSP Data Memory Address
-----------------------------------------------
DM(tx0a_buf + 0) = DM(tx0a_buf + Internal_DAC_L0) /
DM(tx0a_buf + 1) = DM(tx0a_buf + Internal_DAC_L1) /
DM(tx0a_buf + 2) = DM(tx0a_buf + Internal_DAC_L2) /
DM(rx0a_buf + 3) = DM(tx0a_buf + AUX_DAC_L0)
DM(tx0a_buf + 4) = DM(tx0a_buf + Internal_DAC_R0) /
DM(tx0a_buf + 5) = DM(tx0a_buf + Internal_DAC_R1) /
DM(tx0a_buf + 6) = DM(tx0a_buf + Internal_DAC_R3) /
DM(tx0a_buf + 7) = DM(tx0a_buf + AUX_DAC_R0)
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
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