ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 23

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

February 1997
4 Hardware Architecture
4.5 External Memory Interface (EMI)
The external memory interface supports read/write op-
erations from instruction/coefficient memory, data
memory, and memory-mapped I/O devices. The
DSP1628 provides a 16-bit external address bus,
AB[15:0], and a 16-bit external data bus, DB[15:0].
These buses are multiplexed between the internal bus-
es for the instruction/coefficient memory and the data
memory. Four external memory segment enables,
ERAMLO, IO, ERAMHI, and EROM, select the external
memory segment to be addressed.
If a data memory location with an address between
0x4100 and 0x7FFF is addressed, ERAMLO is asserted
low.
If one of the 256 external data memory locations, with
an address greater than or equal to 0x4000, and less
than or equal to 0x40FF, is addressed, IO is asserted
low. IO is intended for memory-mapped I/O.
If a data memory location with an address greater than
or equal to 0x8000 is addressed, ERAMHI is asserted
low. When the external instruction/coefficient memory is
addressed, EROM is asserted low.
The flexibility provided by the programmable options of
the external memory interface (see Table 40, mwait
Register and Table 42, ioc Register) allows the
DSP1628 to interface gluelessly with a variety of com-
mercial memory chips.
Each of the four external memory segments, ERAMLO,
IO, ERAMHI, and EROM, has a number of wait-states
that is programmable (from 0 to 15) by writing to the
mwait register. When the program references memory
in one of the four external segments, the internal multi-
plexer is automatically switched to the appropriate set of
internal buses, and the associated external enable of
ERAMLO, IO, ERAMHI, or EROM is issued. The exter-
nal memory cycle is automatically stretched by the num-
ber of wait-states in the appropriate field of the mwait
register.
When writing to external memory, the RWN pin goes
low for the external cycle. The external data bus,
DB[15:0], is driven by the DSP1628 starting halfway
through the cycle. The data driven on the external data
bus is automatically held after the cycle for one addi-
tional clock period unless an external read cycle imme-
diately follows.
The DSP1628 has one external address bus and one
external data bus for both memory spaces. Since some
instructions provide the capability of simultaneous ac-
cess to both X space and Y space, some provision must
be made to avoid collisions for external accesses. The
DSP1628 has a sequencer that does the external X ac-
cess first, and then the external Y access, transparently
to the programmer. Wait-states are maintained as pro-
grammed in the mwait register. For example, let two in-
Lucent Technologies Inc.
(continued)
structions be executed: the first reads a coefficient from
EROM and writes data to ERAM; the second reads a
coefficient from EROM and reads data from ERAM. The
sequencer carries out the following steps at the external
memory interface: read EROM, write ERAM, read ER-
OM, and read ERAM. Each step is done in sequential
one-instruction cycle steps, assuming zero wait-states
are programmed. Note that the number of instruction
cycles taken by the two instructions is four. Also, in this
case, the write hold time is zero.
The DSP1628 allows writing into external instruction/
coefficient memory. By setting bit 11, WEROM, of the
ioc register (see Table 42), writing to (or reading from)
data memory or memory-mapped I/O asserts the
EROM strobe instead of ERAMLO, IO, or ERAMHI.
Therefore, with WEROM set, EROM appears in both Y
space (replacing ERAM) and X space, in its normal po-
sition.
Bit 14 of the ioc register (see Table 42), EXTROM, may
be used with WEROM to download to a full 64K of ex-
ternal memory. When WEROM and EXTROM are both
asserted, address bit 15 (AB15) is held low, aliasing the
upper 32K of external memory into the lower 32K.
When an access to internal memory is made, the
AB[15:0] bus holds the last valid external memory ad-
dress. Asserting the RSTB pin low 3-states the AB[15:0]
bus. After reset, the AB[15:0] value is undefined.
The leading edge of the memory segment enables can
be delayed by approximately one-half a CKO period by
programming the ioc register (see Table 42). This is
used to avoid a situation in which two devices drive the
data bus simultaneously.
Bits 7, 8, and 13 of the ioc register select the mode of
operation for the CKO pin (see Table 42). Available op-
tions are a free-running unstretched clock, a wait-stated
sequenced clock (runs through two complete cycles
during a sequenced external memory access), and a
wait-stated clock based on the internal instruction cycle.
These clocks drop to the low-speed internal ring oscilla-
tor when SLOWCKI is enabled (see 4.13, Power Man-
agement). The high-to-low transitions of the wait-stated
clock are synchronized to the high-to-low transition of
the free-running clock. Also, the CKO pin provides ei-
ther a continuously high level, a continuously low level,
or changes at the rate of the internal processor clock.
This last option, only available with the small-signal in-
put clock options, enables the DSP1628 CKI input buff-
er to deliver a full-rate clock to other devices while the
DSP1628 itself is in one of the low-power modes.
DSP1628 Digital Signal Processor
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