ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 35

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

February 1997
4 Hardware Architecture
Table 13. Memory-Mapped Registers (continued)
Lucent Technologies Inc.
0x411—0x7FF
Address
0x40e—f
0x407
0x408
0x409
0x40a
0x40b
0x40c
0x40d
0x410
Received Symbol/Channel Tap Register
S1H1
Received Symbol/Channel Tap Register
S0H0
Decoded Symbol Register
DSR
Received Real Signal/Generating Polynomial
ZIG10
Received Imaginary Signal/Generating Polynomial
ZQG32
Generating Polynomial
G54
Minimum Cost Index Register
MIDX
Minimum Accumulated Cost Register
MACH
MACL
Traceback Shift Register
TBSR
Reserved Registers
Register
(continued)
Convolutional decoding case:
MLSE equalization case:
Convolutional decoding case:
MLSE equalization case:
Bit 7:0 is zero.
Bit 15:8 is decoded symbol.
Convolutional case:
MLSE case:
Convolutional case:
MLSE case:
Convolutional case:
MLSE case:
0x040E
Traceback shift register (TBSR)
Reserved.
Bit 7:0 is reserved.
Bit 15:8 is S1.
Bit 7:0 is HQ1.
Bit 15:8 is HI1.
Bit 7:0 is reserved.
Bit 15:8 is S0.
Bit 7:0 is HQ0.
Bit 15:8 is HI0.
Bit 7:0 is G0.
Bit 15:8 is G1.
Bit 9:0 is in-phase part of received signal.
Bit 15:10 is reserved.
Bit 7:0 is G2.
Bit 15:8 is G3.
Bit 9:0 is quadrature-phase part of received signal.
Bit 15:10 is reserved.
Bit 7:0 is G4.
Bit 15:8 is G5.
Bit 15:0 is reserved.
Bit 7:0 is used.
Bit 15:8 is reserved.
Bit 15:8 is zero.
Bit 7:0 is upper byte of the minimum accumulated cost 0x040F.
Bit 15:0 is the lower 2 bytes of the minimum accumulated cost.
Bit 7:0 TBSR.
Bit 15:8 is reserved.
DSP1628 Digital Signal Processor
Register Bit Field
33