ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 42

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

DSP1628 Digital Signal Processor
4 Hardware Architecture
Notes:
The functions in the shaded ovals are bits in the powerc control register. The functions in the nonshaded ovals are bits in the pllc control
register.
Deep sleep is the state arrived at either by a hardware or software stop of the internal processor clock.
The switching of the multiplexers and the synchronous gate is designed so that no partial clocks or glitching will occur.
When the deep sleep state is entered with the ring oscillator selected, the internal processor clock is turned off before the ring oscillator is
powered down.
PLL select is the PLLSEL bit of pllc; PLL powerdown is the PLLEN bit of pllc.
40
CKI2
CKI
STOP
RSTB
INT0
INT1
INT0EN
INT1EN
XTLOFF
HW STOP
NOCK
MASK-PROGRAMMABLE
Figure 11. Power Management Using the powerc and the pllc Registers
CLOCK
CMOS
INPUT
SMALL SIGNAL
CLEAR NOCK
OPTION
SW STOP
CLOCK
OFF
(continued)
PLLSEL
SLEEP
DEEP
f
DISABLE
PLLEN
CKI
PLL
f
VCO/2
OSCILLATOR
SYNC.
SYNC.
GATE
MUX
RING
f
INTERNAL CLOCK
PROCESSOR
INTERNAL
CLOCK
f
SLOW CLOCK
ON
SLOWCKI
Lucent Technologies Inc.
5-4124 (F).c
February 1997
SLEEP
DEEP