ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 88

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

February 1997
10 Timing Characteristics for 2.7 V Operation
The following timing characteristics and requirements are preliminary information and are subject to change. Timing
characteristics refer to the behavior of the device under specified conditions. Timing requirements refer to conditions
imposed on the user for proper operation of the device. All timing data is valid for the following conditions:
T
V
Capacitance load on outputs (C
Output characteristics can be derated as a function of load capacitance (C
All outputs: 0.03 ns/pF
For example, if the actual load capacitance is 30 pF instead of 50 pF, the derating for a rising edge is (30 – 50) pF
x 0.06 ns/pF = 1.2 ns less than the specified rise time or delay that includes a rise time.
Test conditions for inputs:
Test conditions for outputs (unless noted otherwise):
For the timing diagrams, see Table 62 for input clock requirements.
Unless otherwise noted, CKO in the timing diagrams is the free-running CKO.
Lucent Technologies Inc.
A
DD
= –40 C to +85 C (See Section 8.3.)
Rise and fall times of 4 ns or less
Timing reference levels for delays = V
C
Timing reference levels for delays = V
3-state delays measured to the high-impedance state of the output driver
= 3 V
LOAD
= 50 pF; except for CKO, where C
10%, V
at V
IH
for rising edge and at V
SS
= 0 V (See Section 8.3.)
dt/dC
L
L
) = 50 pF, except for CKO, where C
0.07 ns/pF for 10
IH
IH
IL
, V
, V
for falling edge
LOAD
IL
IL
= 20 pF
C
L
100 pF
L
= 20 pF
DSP1628 Digital Signal Processor
L
).
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