ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 76

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

DSP1628 Digital Signal Processor
6 Signal Descriptions
6.2 External Memory Interface
The external memory interface is used to interface the
DSP1628 to external memory and I/O devices. It sup-
ports read/write operations from/to program and data
memory spaces. The interface supports four external
memory segments. Each external memory segment
can have an independent number of software-program-
mable wait-states. One hardware address is decoded,
and an enable line is provided, to allow glueless I/O in-
terfacing.
AB[15:0]
External Memory Address Bus: Output only.
This 16-bit bus supplies the address for read or write
operations to the external memory or I/O. During exter-
nal memory accesses, AB[15:0] retain the value of the
last valid external access.
DB[15:0]
External Memory Data Bus: This 16-bit bidirectional
data bus is used for read or write operations to the ex-
ternal memory or I/O.
RWN
Read/Write Not: When a logic 1, the pin indicates that
the memory access is a read operation. When a logic 0,
the memory access is a write operation.
EXM
External Memory Select: Input only. This signal is
latched into the device on the rising edge of RSTB. The
value of EXM latched in determines whether the internal
ROM is addressable in the instruction/coefficient mem-
ory map. If EXM is low, internal ROM is addressable. If
EXM is high, only external ROM is addressable in the
instruction/coefficient memory map (see Table 5, In-
struction/Coefficient Memory Maps). EXM chooses be-
tween MAP1 or MAP2 and between MAP3 or MAP4.
74
(continued)
EROM
External ROM Enable Signal: Negative assertion.
When asserted, the signal indicates an access to
external program memory (see Table 5, Instruction/
Coefficient Memory Maps). This signal's leading edge
can be delayed via the ioc register (see Table 42).
ERAMHI
External RAM High Enable Signal: Negative asser-
tion. When asserted, the signal indicates an access to
external data memory addresses 0x8000 through
0xFFFF (see Table 6, Data Memory Map). This signal's
leading edge can be delayed via the ioc register (see
Table 42).
ERAMLO
External RAM Low Enable Signal: Negative asser-
tion. When asserted, the signal indicates an access to
external data memory addresses 0x4100 through
0x7FFF (see Table 6, Data Memory Map). This signal's
leading edge can be delayed via the ioc register (see
Table 42).
IO
External I/O Enable Signal: Negative assertion. When
asserted, the signal indicates an access to external data
memory addresses 0x4000 through 0x40FF (see
Table , Data Memory Map). This memory segment is in-
tended for memory-mapped I/O. This signal's leading
edge can be delayed via the ioc register (see Table 42).
Lucent Technologies Inc.
February 1997