ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 55

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

February 1997
5 Software Architecture
Cache Instructions
Cache instructions require one word of program memory. The do instruction executes in one instruction cycle, and
the redo instruction executes in two instruction cycles. (If PC points to external memory, add programmed wait-
states.) Control instructions and long immediate values cannot be stored inside the cache. The instruction formats
are as follows:
do K {
redo K
Table 24. Replacement Table for Cache Instructions
† The assembly-language statement, do cloop (or redo cloop), is used to specify that the number of iterations is to be taken from the cloop
When the cache is used to execute a block of instructions, the cycle timings of the instructions are as follows:
1. In the first pass, the instructions are fetched from program memory and the cycle times are the normal out-of-
2. During pass two through pass K – 1, each instruction is fetched from cache and the in-cache timings apply.
3. During the last (Kth) pass, the block of instructions is fetched from cache and the in-cache timings apply, except
4. If any of the instructions access external memory, programmed wait-states must be added to the cycle counts.
The redo instruction treats the instructions currently in the cache memory as another loop to be executed K times.
Using the redo instruction, instructions are reexecuted from the cache without reloading the cache.
The number of iterations, K, for a do or redo can be set at run time by first moving the number of iterations into the
cloop register (7 bits unsigned), and then issuing the do cloop or redo cloop. At the completion of the loop, the
value of cloop is decremented to 0; hence, cloop needs to be written before each do cloop or redo cloop.
Lucent Technologies Inc.
Replace
register. K is encoded as 0 in the instruction encoding to select cloop.
instr1
instr2
.
.
.
instrN
}
cache values, except for the last instruction in the block of N instructions. This instruction executes in two cycles.
that the timing of the last instruction is the same as if it were out-of-cache.
N
K
Instruction
Encoding
1 to 127
1 to 15
cloop
†
Number of times the instructions are to be executed taken from bits 0—6 of the cloop
register.
Number of times the instructions to be executed is encoded in the instruction.
1 to 15 instructions can be included.
(continued)
Meaning
DSP1628 Digital Signal Processor
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