ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 28

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

DSP1628 Digital Signal Processor
4 Hardware Architecture
4.10 Timer
The interrupt timer is composed of the timerc (control)
register, the timer0 register, the prescaler, and the
counter itself. The timer control register (see Table 35,
timerc Register) sets up the operational state of the tim-
er and prescaler. The timer0 register is used to hold the
counter reload value (or period register) and to set the
initial value of the counter. The prescaler slows the
clock to the timer by a number of binary divisors to allow
for a wide range of interrupt delay periods.
The counter is a 16-bit down counter that can be loaded
with an arbitrary number from software. It counts down
to 0 at the clock rate provided by the prescaler. Upon
reaching 0 count, a vectored interrupt to program ad-
dress 0x08 is issued to the DSP1628, providing the in-
terrupt is enabled (bit 8 of inc and ins registers). The
counter will then either wait in an inactive state for an-
other command from software, or will automatically re-
peat the last interrupting period, depending upon the
state of the RELOAD bit in the timerc register.
When RELOAD is 0, the counter counts down from its
initial value to 0, interrupts the DSP1628, and then
stops, remaining inactive until another value is written to
the timer0 register. Writing to the timer0 register caus-
es both the counter and the period register to be written
with the specified 16-bit number. When RELOAD is 1,
the counter counts down from its initial value to 0, inter-
rupts the DSP1628, automatically reloads the specified
initial value from the period register into the counter,
and repeats indefinitely. This provides for either a single
timed interrupt event or a regular interrupt clock of arbi-
trary period.
The timer can be stopped and started by software, and
can be reloaded with a new period at any time. Its count
value, at the time of the read, can also be read by soft-
ware. Due to pipeline stages, stopping and starting the
timer may result in one inaccurate count or prescaled
period. When the DSP1628 is reset, the bottom 6 bits of
the timerc register and the timer0 register and counter
are initialized to 0. This sets the prescaler to CKO/2
turns off the reload feature, disables timer counting, and
initializes the timer to its inactive state. The act of reset-
ting the chip does not cause a timer interrupt. Note that
the period register is not initialized on reset.
The T0EN bit of the timerc register enables the clock to
the timer. When T0EN is a 1, the timer counts down to-
wards 0. When T0EN is a 0, the timer holds its current
count.
The PRESCALE field of the timerc register selects one
of 16 possible clock rates for the timer input clock (see
Table 35, timerc Register).
Setting the DISABLE bit of the timerc register to a logic
* Frequency of CKO/2 is equivalent to either CKI/2 for the PLL by-
26
passed or related to CKI by the PLL multiplying factors. See
Section 4.13, Clock Synthesis.
(continued)
*
,
1 shuts down the timer and the prescaler for power sav-
ings. Setting the TIMERDIS, bit 4, in the powerc regis-
ter has the same effect of shutting down the timer. The
DISABLE bit and the TIMERDIS bit are cleared by writ-
ing a 0 to their respective registers to restore the normal
operating mode.
4.11 Error Correction Coprocessor
The error correction coprocessor (ECCP) performs full
Viterbi decoding with single instructions for a wide
range of maximum likelihood sequence estimation
(MLSE) equalization and convolutional decoding. The
ECCP operates in parallel with the DSP core, increas-
ing the throughput rate, and single-instruction Viterbi
decoding provides significant code compression re-
quired for a single DSP solution for modern digital cellu-
lar applications.
System Description
The ECCP is a loosely coupled, programmable, internal
coprocessor that operates in parallel with the DSP1600
core. A complete Viterbi decoding for MLSE equaliza-
tion or convolutional decoding is performed with a single
DSP instruction.
The core communicates with the ECCP module via
three interface registers. An address register, ear, is
used to indirectly access the ECCP internal memory-
mapped registers. A data register, edr, works in concert
with the address register to indirectly read from or write
to an ECCP internal memory-mapped register ad-
dressed by the contents of the address register. After
each edr access, the contents of the address register is
postincremented by one. Upon writing an ECCP op
code to instruction register, eir, either MLSE equaliza-
tion, convolutional decoding, a simple traceback opera-
tion, or ECCP reset is invoked.
The mode of operation of the ECCP is set up by writing
appropriate fields of a memory-mapped control register.
In MLSE equalization, the control register may be con-
figured for 2-tap to 6-tap equalization. In convolutional
decoding, the control register may be configured for
constraint lengths 2 through 7 and code rates 1/1
through 1/6. One of two variants of the soft-decoded
output may be programmed, or a hard-decoded output
may be chosen.
Usually, convolutional decoding is performed after
MLSE equalization. For receiver configuration with
MLSE equalization followed by convolutional decoding,
a Manhattan branch metric computation for convolu-
tional decoding may be selected by setting a branch
metric select bit in the control register.
Lucent Technologies Inc.
February 1997