ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 33

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

February 1997
4 Hardware Architecture
Software Architecture
The ECCP registers are grouped into two categories:
the R-field registers and the internal memory-mapped
registers.
R-Field Registers: Three registers (ear, edr, and eir)
are defined in the core instruction set as programmable
registers for executing the ECCP and establishing the
data interface between the ECCP and the core. Re-
served bits are always zero when read and should be
written with zeros to make the program compatible with
future chip revisions.
Address Register (ear): The address register holds
the address of the ECCP internal memory-mapped reg-
isters. Each time the core accesses an internal ECCP
register through edr, the content of the address register
is postincremented by one. During a DSP compound
addressing instruction, the same edr register is access-
ed for both the read and the write operation.
Data Register (edr): The contents of the ECCP internal
memory-mapped registers are indirectly accessed by
the DSP through this register. A write to the data regis-
ter is directed to the ECCP internal register addressed
by the contents of the address register. A read from the
data register fetches the contents of the ECCP internal
register addressed by the address register. Every ac-
cess to the edr autoincrements the address register,
ear.
Instruction Register (eir): Four instructions are de-
fined for the ECCP operation. These instructions will be
executed upon writing appropriate values in the eir reg-
ister. Table 11 indicates the instruction encoding and
their mnemonics.
Table 11. ECCP Instruction Encoding
Lucent Technologies Inc.
eir Value in hex
0005—FFFF
0000
0001
0002
0003
0004
UpdateMLSE
UpdateConv
ResetECCP
Instruction
TraceBack
Reserved
Reserved
(continued)
The UpdateMLSE instruction and the UpdateConv in-
struction each perform an appropriate branch metric
calculation, a complete Viterbi add-compare-select op-
eration, and a concurrent traceback decoding opera-
tion. The TraceBack instruction performs the traceback
decoding alone.
The ResetECCP instruction performs a proper reset op-
eration to initialize various registers as described in Ta-
ble 12.
Table 12. Reset State of ECCP Registers
During periods of ECCP activity, write operations to the
eir and edr registers as well as the read operation of the
edr register by the DSP code will be blocked. The
ECCP address register, ear, however, can be read or
written during ECCP operation to set up the ECCP ad-
dress for the next edr access after the completion of the
ECCP instruction. Note that the eir register can be read
during ECCP activity.
Register
ECON
MACH
MACL
MIDX
SYC
ear
DSP1628 Digital Signal Processor
eir
—
0xf (on pin reset)
Reset State
0xffff
0x4
0x0
0x0
0x0
0x0
0xff
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