ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 29

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

February 1997
4 Hardware Architecture
In wideband low data rate applications, additive white
Gaussian noise (AWGN) is the principle channel impair-
ment, and Euclidean branch metric computation for
convolutional decoding is selected by resetting the
branch metric select bit to zero.
A traceback-length register is provided for programming
the traceback decode length.
A block diagram of the coprocessor and its interface to
the DSP1600 core is shown in the following figure:
Figure 7. Error Correction Coprocessor Block
The ECCP internal registers are accessed indirectly
through the address and data registers, ear and edr.
The control register, ECON, and the traceback length
register, TBLR, are used to program the operating
mode of the ECCP. The symbol registers (S0H0—
S5H5, ZIG10, ZQG32), the generating polynomial reg-
isters (ZIG10, ZQG32, G54), and the channel impulse
registers (S0H0—S5H5) are used as input to the ECCP
for MLSE or convolutional decoding. Following a Viterbi
decoding operation, the decoded symbol is read out of
the decoded symbol register, DSR. All internal states of
these memory-mapped registers are accessible and
controllable by the DSP program. During periods of si-
Lucent Technologies Inc.
EOVF
EREADY
EBUSY
IDB
RAM4
ear
edr
Diagram/Programming Model
eir
CONTROL UNIT
ECON
ECCP
(continued)
TRACEBACK UNIT
BRANCH METRIC
SiHi, i = 0, . . . ,5
UPDATE UNIT
NS[63:0]
PS[63:0]
ZQG32
MACH
ZIG10
MACL
TBLR
TBSR
UNIT
MDX
SYC
DSR
G54
5-4500 (F)
multaneous DSP-ECCP activity, however, ECCP inter-
nal edr registers as well as the shared bank of RAM,
RAM4, are not accessible to the user's DSP code.
Branch Metric Unit: The branch metric unit of the
ECCP performs full-precision real and complex arith-
metic for computing 16-bit incremental branch metrics
required for MLSE equalization and convolutional de-
coding.
MLSE Branch Metric Unit: To generate the estimated
received complex signal at instance n, E(n, k) = EI(n, k)
+ j EQ(n, k), at the receiver, all possible states, k = 0 to
2C – 1 – 1, taking part in the Viterbi state transition are
convolved with the estimated channel impulse re-
sponse, H(n) = [h(n), h(n – 1), h(n – 2), . . . , h(n – C +
1)] T, where the constraint length C = {2 to 6}. Each in-
phase and quadrature-phase part of the channel tap,
h(n) = hI(n) + j hQ(n), is quantized to an 8-bit 2's com-
plement number.
The channel estimates are normalized prior to loading
into the ECCP such that the worst-case summation of
the hI(n) or hQ(n) are confined within a 10-bit 2's com-
plement number. The in-phase and quadrature-phase
parts of the received complex signal Z(n) = ZI(n) + j
ZQ(n) are also confined within a10-bit 2's complement
number. The Euclidean branch metric associated with
each of the 2C state transitions is calculated as:
BM(n, k) = XI(n, k)2 + XQ(n, k)2
where
XI(n, k) = abs{ZI(n) – EI(n, k)}
and
XQ(n, k) = abs{ZQ(n) – EQ(n, k)}
The absolute values of the difference signal are saturat-
ed at level 0xFF. The sixteen most significant bits of this
17-bit incremental branch metric are retained for the
add-compare-select operation of the Viterbi algorithm.
The in-phase and quadrature-phase parts of the re-
ceived complex signal are stored in ZIG10 and ZQG32
registers, respectively. The complex estimated channel
taps H5 through H0 are stored in S5H5 through S0H0
registers, such that the in-phase part of the channel oc-
cupies the upper byte and the quadrature-phase part of
the channel occupies the lower byte.
Convolutional Branch Metric Unit: Two types of distance
computation are implemented for convolutional decod-
ing. Convolutional decoding over a Gaussian channel is
supported with Euclidean distance measure for rate 1/1
and 1/2 convolutional encoding. Convolutional decod-
ing preceded by the MLSE equalization or other linear/
nonlinear equalization is supported with Manhattan dis-
tance measure for rate 1/1 through 1/6 convolutional
encoding.
DSP1628 Digital Signal Processor
27