ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 84

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

February 1997
9 Electrical Characteristics and Requirements
Table 63. PLL Electrical Specifications, VCO Frequency Ranges
Table 64. PLL Electrical Specifications and pllc Register Settings
Note 1.
Note 2.
Lucent Technologies Inc.
VCO frequency range
Input Jitter at CKI
23—24 2.7 V – 3.3 V
21—22 2.7 V – 3.3 V
19—20 2.7 V – 3.3 V
16—18 2.7 V – 3.3 V
12—15 2.7 V – 3.3 V
8—11
2—7
(V
M
DD
The M and N counter values in the pllc register must be set so that the VCO will operate in the appro-
priate range (see Table 63). Choose the lowest value of N and then the appropriate value of M for
f
Lock-in time represents the time following assertion of the PLLEN bit of the pllc register during which
the PLL output clock is unstable. The DSP must operate from the 1X CKI input clock or from the slow
ring oscillator while the PLL is locking. Completion of the lock-in interval is indicated by assertion of the
LOCK flag.
= 3 V 10%)
INTERNAL CLOCK
2.7 V – 3.3 V
2.7 V – 3.3 V
Parameter
V
DD
=
f
CKI
x (M/(2N)) =
pllc13
(ICP)
1
1
1
1
1
1
1
Reserved
f
VCO
Symbol
pllc12
f
/2.
VCO
0
0
0
0
0
0
0
—
pllc[11:8]
(LF[3:0])
1011
1010
1001
1000
0111
0110
0100
Min
50
—
Typical Lock-in Time ( s)
Max
160
200
(continued)
(See Note 2.)
DSP1628 Digital Signal Processor
ps-rms
MHz
Unit
30
30
30
30
30
30
30
Note
—
1
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