ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 87

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

DSP1628 Digital Signal Processor
9 Electrical Characteristics and Requirements
Table 65. Power Dissipation and Wake-Up Latency (continued)
* T = CKI clock cycle for 1X input clock option or T = CKI clock cycle divided by M/(2N) for PLL clock option (see Section 4.12).
†
The power dissipation listed is for internal power dissipation only. Total power dissipation can be calculated on the
basis of the application by adding C x V
the output frequency.
Power dissipation due to the input buffers is highly dependent on the input voltage level. At full CMOS levels, es-
sentially no dc current is drawn. However, for levels between the power supply rails, especially at or near the thresh-
old of V
of the input and I/O buffers are designed to remain at full CMOS levels when not driven by the DSP), it is still rec-
ommended that unused input and I/O pins be tied to V
biguities. Further, if I/O pins are tied high or low, they should be pulled fully to V
WARNING: The device needs to be clocked for at least six CKI cycles during reset after powerup. Other-
85
Sleep with Slow Internal Clock
Software Stop
Software Stop
Hardware Stop (STOP = V
Hardware Stop (STOP = V
t
L
(Unused inputs at V
= PLL lock time (see Table 64).
PLL Disabled During STOP
PLL Disabled During STOP
PLL Disabled During STOP
PLL Disabled During Sleep
PLL Enabled During STOP
alf[15] = 1, ioc = 0x0180
Small Signal Disabled
powerc[15:12] = 0011
powerc[15:12] = 1111
powerc[15:12] = 0000
powerc[15:12] = 0000
DD
powerc[15:14] = 11,
Operating Mode
/2, high currents can flow. Although input and I/O buffers may be left untied (since the input voltage levels
wise, high currents may flow.
Small Signal
Small Signal
Small Signal
Small Signal
DD
or V
CMOS
CMOS
CMOS
SS
SS
V
DD=
)
)
SS)
I/O Units ON, ECCP OFF
powerc[7:4,0] = 0x01
Typical Power Dissipation (mW)
DD
0.060
0.060
0.060
0.40
1.20
3 V
2.5
3.6
2
x f for each output, where C is the additional load capacitance and f is
I/O Units OFF, ECCP OFF
SS
powerc[7:4,0] = 0xF1
or V
0.060
0.060
0.060
0.30
1.20
3 V
2.5
3.6
DD
through a 10 k resistor to avoid application am-
(continued)
During Wake State)
(PLL Not Used
SS
20 s
20 s
3T*
3T*
3T*
3T*
3T*
3 V
or V
Wake-Up Latency
DD
Lucent Technologies Inc.
.
During Wake State)
February 1997
20 s + t
20 s + t
(PLL Used
3T* + t
3T*
3T*
3 V
—
—
L †
L †
L †