ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 48

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

DSP1628 Digital Signal Processor
5 Software Architecture
5.1 Instruction Set
The DSP1628 processor has seven types of instruc-
tions: multiply/ALU, special function, control, F3 ALU,
BMU, cache, and data move. The multiply/ALU instruc-
tions are the primary instructions used to implement sig-
nal processing algorithms. Statements from this group
can be combined to generate multiply/accumulate, log-
ical, and other ALU functions and to transfer data be-
tween memory and registers in the data arithmetic unit.
The special function instructions can be conditionally
executed based on flags from the previous ALU or BMU
operation, the condition of one of the counters, or the
value of a pseudorandom bit in the DSP1628 device.
Special function instructions perform shift, round, and
complement functions. The F3 ALU instructions enrich
the operations available on accumulators. The BMU in-
structions provide high-performance bit manipulation.
The control instructions implement the goto and call
commands. Control instructions can also be executed
conditionally. Cache instructions are used to implement
low-overhead loops, conserve program memory, and
decrease the execution time of certain multiply/ALU in-
structions. Data move instructions are used to transfer
data between memory and registers or between accu-
mulators and registers. See the DSP1611/17/18/27
Digital Signal Processor Information Manual for a de-
tailed description of the instruction set.
The following operators are used in describing the in-
struction set:
*
+
–
>>
>>> Logical right shift
<<
<<< Logical left shift
|
&
^
:
~
† These are 36-bit operations. One operand is 36-bit data in an accu-
46
mulator; the other operand may be 16, 32, or 36 bits.
16 x 16-bit –> 32-bit multiplication or register-in-
direct addressing when used as a prefix to an ad-
dress register or denotes direct addressing when
used as a prefix to an immediate
36-bit addition
36-bit subtraction
Arithmetic right shift
Arithmetic left shift
36-bit bitwise OR
36-bit bitwise AND
36-bit bitwise EXCLUSIVE OR
Compound address swapping, accumulator
shuffling
One's complement
†
†
†
†
†
Object Code Compatibility
The DSP1628 is object code compatible with the
DSP1618 with the following exceptions:
Multiply/ALU Instructions
Note that the function statements and transfer state-
ments in Table 17 are chosen independently. Any func-
tion statement (F1) can be combined with any transfer
statement to form a valid multiply/ALU instruction. If ei-
ther statement is not required, a single statement from
either column also constitutes a valid instruction. The
number of cycles to execute the instruction is a function
of the transfer column. (An instruction with no transfer
statement executes in one instruction cycle.) Whenever
PC, pt, or rM is used in the instruction and points to ex-
ternal memory, the programmed number of wait-states
must be added to the instruction cycle count. All multi-
ply/ALU instructions require one word of program mem-
ory. The no-operation (nop) instruction is a special case
encoding of a multiply/ALU instruction and executes in
one cycle. The assembly-language representation of a
nop is either nop or a single semicolon.
ECCP user flag, EBUSY, which indicates error
correction coprocessor activity, has changed its
condition field.
The EBUSY flag is used in conjunction with the
if CON F2 or if CON goto/call/return instructions
to monitor the ECCP operation. The object code
corresponding to ifc EBUSY, for example, must be
modified to reflect the change in condition codes.
Alternately, the source code can be assembled using
DSP1628 development tools.
The SIO and SIO2 interrupts (IBF, IBF2, OBE, and
OBE2) are cleared one instruction cycle AFTER
reading or writing the serial data registers, (sdx[in],
sdx2[in], sdx[out], or sdx2[out]). To account for this
added latency, the user must ensure that a single
instruction (NOP or any other valid DSP16XX
instruction) follows the sdx register read or write
instruction prior to exiting an interrupt service routine
(via an ireturn or goto pi instruction) or before check-
ing the ins register for the SIO flag status. Adding
this instruction ensures that interrupts are not
reported incorrectly following an ireturn or that stale
flags are not read from the ins register. Refer to
TECHNICAL ADVISORY #23.
11100
11101
CON
Condition
DSP1618
reserved
ebusy
Lucent Technologies Inc.
DSP1628
February 1997
ebusy
lock