ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 61

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

February 1997
5 Software Architecture
Table 32. Parallel Host Interface Control (phifc) Register
Table 33. Interrupt Control (inc) Register
* JINT is a JTAG interrupt and is controlled by the HDS. It may be made unmaskable by the Lucent Technologies development system tools.
Encoding: A 0 disables an interrupt; a 1 enables an interrupt.
Table 34. Interrupt Status (ins) Register
Encoding: A 0 indicates no interrupt. A 1 indicates an interrupt has been recognized and is pending or being ser-
Lucent Technologies Inc.
Field
Field
Field
Bit
Bit
Bit
PFLAGSEL
PSTROBE
PSOBEF
PBSELF
PMODE
PSTRB
PFLAG
Field
JINT*
JINT
15
15
Reserved
viced. If a 1 is written to bits 4, 5, 8, 12, or 13 of ins, the corresponding interrupt is cleared.
15—7
rsrvd
rsrvd
14
14
Value
EREADY
EREADY
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PSOBEF
13
13
6
(continued)
8-bit data transfers.
16-bit data transfers.
Intel protocol: PIDS and PODS data strobes.
Motorola protocol: PRWN and PDS data strobes.
When PSTROBE = 1, PODS pin (PDS) active-low.
When PSTROBE = 1, PODS pin (PDS) active-high.
In either mode, PBSEL pin = 0 -> pdx0 low byte. See Table 7.
If PMODE = 0, PBSEL pin = 1 -> pdx0 low byte.
If PMODE = 1, PBSEL pin = 0 -> pdx0 high byte.
PIBF and POBE pins active-high.
PIBF and POBE pins active-low.
Normal.
PIBF flag ORed with POBE flag and output on PIBF pin; POBE pin un-
changed (output buffer empty).
Normal.
POBE flag as read through PSTAT register is active-low.
EOVF
EOVF
12
12
PFLAGSEL
rsrvd
rsrvd
5
11
11
OBE2
OBE2
10
10
PFLAG
IBF2
IBF2
4
9
9
TIME rsrvd
TIME rsrvd
Description
PBSELF
8
8
3
DSP1628 Digital Signal Processor
7—6
7—6
PSTRB
INT[1:0]
INT[1:0]
5—4
5—4
2
PIBF POBE
PIBF POBE
PSTROBE
3
3
1
2
2
OBE
OBE
PMODE
1
1
0
IBF
IBF
0
0
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