tmp86fh09amg TOSHIBA Semiconductor CORPORATION, tmp86fh09amg Datasheet - Page 120

• Manufacturer Part Number: tmp86fh09amg
• Description: 8 Bit Microcontroller Tlcs-870/c Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

11.2
SEI Registers
11.2
Read-modify-write instruction are prohibited
11.2.1
(002AH)
SECR
(SEDR) which are used to set up the SEI system and enable/disable SEI operation.
11.2.1.1
The SEI interface has the SEI Control Register (SECR), SEI Status Register (SESR), and SEI Data Register
SEI Registers
Note 1: If mode fault detection is enabled, an interrupt is generated when the MODF flag (SESR<MODF>) is set.
Note 2: SEI operation can only be disabled after transfer is completed. Before the SEI can be used, the each Port Con-
Note 3: Master/slave settings must be made before enabling SEI operation (This means that the SECR<MSTR> bit
SEI Control Register (SECR)
MODE
(1)
MODE
MSTR
CPOL
CPHA
7
SEE
BOS
SER
Transfer rate
when the SEI is operating as the master.
trol Register and Output Latch Control must be set for the SEI function (In case P0 port, P0OUTCR and P0DR).
When using the SEI as the master, set the SECR<SEE> bit to “1” (to enable SEI operation) and then place trans-
mit data in the SEDR register. This initiates transmission/reception.
must first be set before setting the SECR<SEE> bit to “1”).
The table below shows the relationship between settings of the SER bit and transfer bit rates
Master mode (Transfer rate = fc/Internal clock divide ratio (unit: bps))
SEE
6
Table 11-1 SEI Transfer Rate
Mode fault detection (Note1)
SEI operation (Note2)
Bit order selection
Mode selection (Note3)
Clock polarity
Clock phase
Selects SEI transfer rate
SER
00
01
10
11
BOS
5
Internal Clock Divide Ratio of SEI
MSTR
4
16
64
4
8
CPOL
3
Page 110
0: Enables mode fault detection
1: Disables mode fault detection
It is available in Master mode only.
(Note: Make sure to set <MODE> bit to "1" for disabling Mode fault de-
tection
0: Disables SEI operation
1: Enables SEI operation
0: Transmitted beginning with the MSB (bit 7) of SEDR register
1: Transmitted beginning with the LSB (bit 0) of SEDR register
0: Sets SEI for slave
1: Sets SEI for master
0: Selects active-“H” clock. SCLK remains “L” when IDLE.
1: Selects active-“L” clock. SCLK remains “H” when IDLE.
Selects clock phase. For details, refer to Section “SEI Transfer For-
mats”.
00: Divide-by-4
01: Divide-by-8
10: Divide-by-16
11: Divide-by-64
CPHA
2
Transfer Rate when fc = 16 MHz
1
SER
250 kbps
4 Mbps
2 Mbps
1 Mbps
0
(Initial value: 0000 0100)
TMP86FH09AMG
R/W