tmp86fh09amg TOSHIBA Semiconductor CORPORATION, tmp86fh09amg Datasheet - Page 33

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tmp86fh09amg

Manufacturer Part Number
tmp86fh09amg
Description
8 Bit Microcontroller Tlcs-870/c Series
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet

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2.2.4.3
base timer control register (TBTCR). The following status is maintained during IDLE0 and SLEEP0
modes.
IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time
IDLE0 and SLEEP0 modes (IDLE0, SLEEP0)
Note:Before starting IDLE0 or SLEEP0 mode, be sure to stop (Disable) peripherals.
1. Timing generator stops feeding clock to peripherals except TBT.
2. The data memory, CPU registers, program status word and port output latches are all held in
3. The program counter holds the address 2 ahead of the instruction which starts IDLE0 and
the status in effect before IDLE0 and SLEEP0 modes were entered.
SLEEP0 modes.
(Normal release mode)
Figure 2-12 IDLE0 and SLEEP0 Modes
No
No
No
No
CPU and WDT are halted
Execution of the instruction
Page 23
which follows the IDLE0,
Starting IDLE0, SLEEP0
Stopping peripherals
Interrupt processing
SLEEP0 modes start
modes by instruction
TBTCR<TBTEN>
by instruction
TBT interrupt
source clock
Reset input
IMF = "1"
instruction
enable
falling
= "1"
edge
TBT
Yes
Yes
Yes
No
Yes (Interrupt release mode)
Yes
Reset
TMP86FH09AMG

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