tmp86fh09amg TOSHIBA Semiconductor CORPORATION, tmp86fh09amg Datasheet - Page 66

• Manufacturer Part Number: tmp86fh09amg
• Description: 8 Bit Microcontroller Tlcs-870/c Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

7.2
Watchdog Timer Control
Example :Setting the watchdog timer detection time to 2
7.2
7.2.1
dog timer is automatically enabled after the reset release.
Watchdog Timer Control
The watchdog timer is controlled by the watchdog timer control registers (WDTCR1 and WDTCR2). The watch-
Within 3/4 of WDT
detection time
Within 3/4 of WDT
detection time
dog timer output is activated by the binary-counter overflow unless the binary counters are cleared. When
WDTCR1<WDTOUT> is set to “1” at this time, the reset request is generated and then internal hardware is in-
itialized. When WDTCR1<WDTOUT> is set to “0”, a watchdog timer interrupt (INTWDT) is generated.
SLEEP mode, and automatically restarts (continues counting) when the STOP/IDLE/SLEEP mode is inactiva-
ted.
Malfunction Detection Methods Using the Watchdog Timer
The CPU malfunction is detected, as shown below.
If the CPU malfunctions such as endless loops or the deadlock conditions occur for some reason, the watch-
The watchdog timer temporarily stops counting in the STOP mode including the warm-up or IDLE/
Note:The watchdog timer consists of an internal divider and a two-stage binary counter. When the clear
1. Set the detection time, select the output, and clear the binary counter.
2. Clear the binary counter repeatedly within the specified detection time.
code 4EH is written, only the binary counter is cleared, but not the internal divider. The minimum bina-
ry-counter overflow time, that depends on the timing at which the clear code (4EH) is written to the
WDTCR2 register, may be 3/4 of the time set in WDTCR1<WDTT>. Therefore, write the clear code us-
ing a cycle shorter than 3/4 of the time set to WDTCR1<WDTT>.
LD
LD
LD
:
:
LD
:
:
LD
(WDTCR2), 4EH
(WDTCR1), 00001101B
(WDTCR2), 4EH
(WDTCR2), 4EH
(WDTCR2), 4EH
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/fc [s], and resetting the CPU malfunction detection
: Clears the binary counters.
: WDTT ← 10, WDTOUT ← 1
: Clears the binary counters (always clears immediately before and
after changing WDTT).
: Clears the binary counters.
: Clears the binary counters.
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