tmp86fh09amg TOSHIBA Semiconductor CORPORATION, tmp86fh09amg Datasheet - Page 96

• Manufacturer Part Number: tmp86fh09amg
• Description: 8 Bit Microcontroller Tlcs-870/c Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

9.3
Function
9.3.2
9.3.3
TC4CR<TC4S>
Internal
Source Clock
Counter
TTREG4
INTTC4 interrupt request
TTREG4
INTTC4 interrupt request
TC4CR<TC4S>
TC4 pin input
Counter
pin. When a match between the up-counter and the TTREGj value is detected, an INTTCj interrupt is gener-
ated and the up-counter is cleared. After being cleared, the up-counter restarts counting at the falling edge of
the input pulse to the TCj pin. Two machine cycles are required for the low- or high-level pulse input to the
TCj pin. Therefore, a maximum frequency to be supplied is fc/2
and fs/2
ter and the TTREGj value is detected, the logic level output from the PDOj pin is switched to the opposite
state and the up-counter is cleared. The INTTCj interrupt request is generated at the time. The logic state oppo-
site to the timer F/Fj logic level is output from the PDOj pin. An arbitrary value can be set to the timer F/Fj
by TCjCR<TFFj>. Upon reset, the timer F/Fj value is initialized to 0.
8-Bit Event Counter Mode (TC3, 4)
8-Bit Programmable Divider Output (PDO) Mode (TC3, 4)
Note 1: In the event counter mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj and PPGj pins may out-
Note 2: In the event counter mode, do not change the TTREGj setting while the timer is running. Since TTREGj
Note 3: j = 3, 4
In the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the TCj
This mode is used to generate a pulse with a 50% duty cycle from the PDOj pin.
In the PDO mode, the up-counter counts up using the internal clock. When a match between the up-coun-
To use the programmable divider output, set the output latch of the I/O port to 1.
4
Hz in the SLOW1/2 or SLEEP1/2 mode.
put pulses.
is not in the shift register configuration in the event counter mode, the new value programmed in
TTREGj is in effect immediately after the programming. Therefore, if TTREGj is changed while the timer
is running, an expected operation may not be obtained.
Figure 9-3 8-Bit Event Counter Mode Timing Chart (TC4)
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Figure 9-2 8-Bit Timer Mode Timing Chart (TC4)
0
n
n
1
1
2
3
2
Match detect
Match detect
n-1
Page 86
n-1
n 0
n 0
Counter clear
Counter
clear
1
1
2
2
Match detect
4
Match detect
Hz in the NORMAL1/2 or IDLE1/2 mode,
n-1
n-1
n
n
0
0
Counter
clear
1
Counter clear
1
2
TMP86FH09AMG
2
0
0