tmp86fh09amg TOSHIBA Semiconductor CORPORATION, tmp86fh09amg Datasheet - Page 34

• Manufacturer Part Number: tmp86fh09amg
• Description: 8 Bit Microcontroller Tlcs-870/c Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

2.2
System Clock Controller
(1)
(2)
Note:IDLE0 and SLEEP0 mode s start/release without reference to TBTCR<TBTEN> setting.
TBTCR<TBTCK>. After the falling edge is detected, the program operation is resumed from the in-
struction following the IDLE0 and SLEEP0 mode s start instruction. Before starting the IDLE0 or
SLEEP0 mode, when the TBTCR<TBTEN> is set to “1”, INTTBT interrupt latch is set to “1”.
TBTCR<TBTCK> and INTTBT interrupt processing is started.
・ Start the IDLE0 and SLEEP0 mode s
・ Release the IDLE0 and SLEEP0 mode s
Note 1: Because returning from IDLE0, SLEEP0 to NORMAL1, SLOW1 is executed by the asynchro-
Note 2: When a watchdog timer interrupt is generated immediately before IDLE0/SLEEP0 mode is star-
IDLE0 and SLEEP0 mode s are released by the source clock falling edge, which is setting by the
IDLE0 and SLEEP0 mode s are released by the source clock falling edge, which is setting by the
Interrupt release mode (IMF・EF6・TBTCR<TBTEN> = “1”)
Normal release mode (IMF・EF6・TBTCR<TBTEN> = “0”)
flag of TBT and TBTCR<TBTEN>.
cleared to “0” and the operation mode is returned to the mode preceding IDLE0 and SLEEP0
mode s. Before starting the IDLE0 or SLEEP0 mode, when the TBTCR<TBTEN> is set to
“1”, INTTBT interrupt latch is set to “1”.
ter releasing reset, the operation mode is started from NORMAL1 mode.
Stop (Disable) peripherals such as a timer counter.
To start IDLE0 and SLEEP0 mode s, set SYSCR2<TGHALT> to “1”.
IDLE0 and SLEEP0 mode s include a normal release mode and an interrupt release mode.
These modes are selected by interrupt master flag (IMF), the individual interrupt enable
After releasing IDLE0 and SLEEP0 mode s, the SYSCR2<TGHALT> is automatically
IDLE0 and SLEEP0 mode s can also be released by inputting low level on the RESET pin. Af-
nous internal clock, the period of IDLE0, SLEEP0 mode might be the shorter than the period set-
ting by TBTCR<TBTCK>.
ted, the watchdog timer interrupt will be processed but IDLE0/SLEEP0 mode will not be started.
Page 24
TMP86FH09AMG