mc9s12ne64 Freescale Semiconductor, Inc, mc9s12ne64 Datasheet - Page 120

• Manufacturer Part Number: mc9s12ne64
• Description: Hcs12 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Chapter 3 Port Integration Module (PIM9NE64V1)
3.3.2.3.2
Read:Anytime.
Write:Never, writes to this register have no effect.
This register always reads back the status of the associated pins. This also can be used to detect overload
or short circuit conditions on output pins.
3.3.2.3.3
Read:Anytime.
Write:Anytime.
This register configures each port G pin as either input or output.
DDRG[7:0] — Data Direction Port G
If the EMAC MII external interface is enabled, the pins G[6:0] are forced to be inputs and DDRG has no
effect on the them. Please refer to the EMAC block description chapter for details.
The DDRG bits revert to controlling the I/O direction of a pin when the EMAC MII external interface is
disabled.
Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTG
or PTIG registers, when changing the DDRG register.
120
1 = Associated pin is configured as output.
0 = Associated pin is configured as input.
Module Base + $11
Module Base + $12
Reset:
Reset:
Read:
Read:
Write:
Write:
Input Register (PTIG)
Data Direction Register (DDRG)
DDRG7
PTIG7
Bit 7
Bit 7
—
0
= Reserved or unimplemented
DDRG6
Figure 3-17. Port G Data Direction Register (DDRG)
PTIG6
—
6
6
0
Figure 3-16. Port G Input Register (PTIG)
MC9S12NE64 Data Sheet, Rev. 1.1
DDRG5
PTIG5
—
5
5
0
DDRG4
PTIG4
—
4
4
0
DDRG3
PTIG3
—
3
3
0
DDRG2
PTIG2
—
2
2
0
DDRG1
PTIG1
—
1
1
0
Freescale Semiconductor
DDRG0
PTIG0
Bit 0
Bit 0
—
0