mc9s12ne64 Freescale Semiconductor, Inc, mc9s12ne64 Datasheet - Page 433

• Manufacturer Part Number: mc9s12ne64
• Description: Hcs12 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

1
2
16.3.2.8
Read: Anytime
Write: Writes have no effect
Reset: Defined at chip integration, see device overview section.
The MEMSIZ1 register reflects the state of the FLASH or ROM physical memory space and paging
switches at the core boundary which are configured at system integration. This register allows read
visibility to the state of these switches.
Freescale Semiconductor
ROM_SW[1:0]
PAG_SW[1:0]
The RAM Reset BASE Address is based on the reset value of the INITRM register, 0x0009.
Alignment of the Allocated RAM space within the RAM mappable region is dependent on the value of RAMHAL.
Reset
ram_sw2:ram_sw0
Field
7:6
1:0
W
R ROM_SW1
101
110
111
Memory Size Register 1 (MEMSIZ1)
—
Allocated System FLASH or ROM Physical Memory Space — The allocated system FLASH or ROM
physical memory space is as given in
Allocated Off-Chip FLASH or ROM Memory Space — The allocated off-chip FLASH or ROM memory space
size is as given in
7
As stated, the bits in this register provide read visibility to the system
physical memory space allocations defined at system integration. The actual
array size for any given type of memory block may differ from the allocated
size. Please refer to the device overview chapter for actual sizes.
= Unimplemented or Reserved
ROM_SW0
—
Table 16-9. Allocated RAM Memory Space (continued)
6
RAM Space
Figure 16-10. Memory Size Register 1 (MEMSIZ1)
Allocated
12K bytes
14K bytes
16K bytes
Table
Table 16-10. MEMSIZ0 Field Descriptions
16-12.
MC9S12NE64 Data Sheet, Rev. 1.1
—
0
5
Mappable Region
Table
16K bytes
16K bytes
16K bytes
NOTE
—
0
4
16-11.
RAM
Description
2
2
—
0
3
RAM[15:14]
RAM[15:14]
RAM[15:14]
Bits Used
INITRM
—
0
2
Memory Map and Register Definition
PAG_SW1
—
1
Base Address
RAM Reset
0x1000
0x0800
0x0000
PAG_SW0
—
0
1
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