mc9s12ne64 Freescale Semiconductor, Inc, mc9s12ne64 Datasheet - Page 196

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mc9s12ne64

Manufacturer Part Number
mc9s12ne64
Description
Hcs12 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Chapter 6 Timer Module (TIM16B4CV1)
6.3.2.13
TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write the bit
to one.
Read: Anytime
Write: Used in clearing mechanism (set bits cause corresponding bits to be cleared).
Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set.
6.3.2.14
Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the
free-running counter when a defined transition is sensed by the corresponding input capture edge detector
or to trigger an output action for output compare.
Read: Anytime
196
Reset
Field
TOF
7
W
Reset
R
Reset
W
R
W
R
TOF
Timer Overflow Flag — Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000. This bit is cleared
automatically by a write to the TFLG2 register with bit 7 set. (See also TCRE control bit explanation.)
Main Timer Interrupt Flag 2 (TFLG2)
Timer Input Capture/Output Compare Registers High and Low 4–7
(TCxH and TCxL)
0
7
Bit 15
Figure 6-20. Timer Input Capture/Output Compare Register x High (TCxH)
15
Bit 7
Figure 6-21. Timer Input Capture/Output Compare Register x Low (TCxL)
0
0
7
Unimplemented or Reserved
0
0
6
Bit 14
14
Bit 6
Figure 6-19. Main Timer Interrupt Flag 2 (TFLG2)
0
0
6
Table 6-16. TRLG2 Field Descriptions
MC9S12NE64 Data Sheet, Rev. 1.1
0
0
5
Bit 13
11
Bit 5
0
0
5
Bit 12
0
0
4
12
Bit 4
0
0
4
Description
Bit 11
0
0
3
11
Bit 3
0
0
3
Bit 10
0
0
2
10
Bit 2
0
0
2
Freescale Semiconductor
Bit 9
0
0
1
Bit 1
0
9
0
1
Bit 8
0
0
Bit 0
0
0
0
0
0

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