mc9s12ne64 Freescale Semiconductor, Inc, mc9s12ne64 Datasheet - Page 270

• Manufacturer Part Number: mc9s12ne64
• Description: Hcs12 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Chapter 9 Serial Peripheral Interface (SPIV3)
9.3.2.4
Read: anytime
Write: has no effect
9.3.2.5
Read: anytime; normally read only after SPIF is set
Write: anytime
270
SPTEF
Reset
Reset
MODF
Field
SPIF
7
5
4
W
W
R
R
SPIF
SPIF Interrupt Flag — This bit is set after a received data byte has been transferred into the SPI Data Register.
This bit is cleared by reading the SPISR register (with SPIF set) followed by a read access to the SPI Data
Register.
0 Transfer not yet complete
1 New data copied to SPIDR
SPI Transmit Empty Interrupt Flag — If set, this bit indicates that the transmit data register is empty. To clear
this bit and place data into the transmit data register, SPISR has to be read with SPTEF = 1, followed by a write
to SPIDR. Any write to the SPI Data Register without reading SPTEF = 1, is effectively ignored.
0 SPI Data register not empty
1 SPI Data register empty
Mode Fault Flag — This bit is set if the SS input becomes low while the SPI is configured as a master and mode
fault detection is enabled, MODFEN bit of SPICR2 register is set. Refer to MODFEN bit description in
Section 9.3.2.2, “SPI Control Register 2 (SPICR2).”
Register (with MODF set) followed by a write to the SPI Control Register 1.
0 Mode fault has not occurred.
1 Mode fault has occurred.
Bit 7
SPI Status Register (SPISR)
SPI Data Register (SPIDR)
0
0
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
0
0
6
0
6
6
Figure 9-6. SPI Status Register (SPISR)
Figure 9-7. SPI Data Register (SPIDR)
Table 9-8. SPISR Field Descriptions
SPTEF
MC9S12NE64 Data Sheet, Rev. 1.1
1
5
0
5
5
MODF
0
4
0
4
4
Description
The flag is cleared automatically by a read of the SPI Status
0
0
3
0
3
3
0
0
2
0
2
2
Freescale Semiconductor
0
0
2
0
1
1
Bit 0
0
0
0
0
0