mc9s12ne64 Freescale Semiconductor, Inc, mc9s12ne64 Datasheet - Page 355

• Manufacturer Part Number: mc9s12ne64
• Description: Hcs12 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

RESET — EPHY Reset
LOOPBACK — Digital Loopback Mode
DATARATE — Speed Selection
ANE — Auto-Negotiation Enable
PDWN — Power Down
ISOL — Isolate
Freescale Semiconductor
Resetting a port is accomplished by setting this bit to 1.
Determines Digital Loopback Mode
The link speed will be selected either through the auto-negotiation process or by manual speed
selection. ANE allows manual speed selection while it is set to 0. While auto-negotiation is enabled,
DATARATE can be read or written but its value is not required to reflect speed of the link.
The ANE bit determines whether the A/N process is enabled. When auto-negotiation is disabled,
DATARATE and DPLX determine the link configuration. While auto-negotiation is enabled, bits
DATARATE and DPLX do not affect the link.
When this bit is set, the port is placed in a low power consumption mode.
1 = The PHY will reset the port’s status and registers to the default values. The PHY will also reset
0 = No effect
1 = Enables digital loopback mode. Port will be placed in loopback mode. Loopback mode will
0 = Disables digital loopback mode
1 = While auto-negotiation is disabled, selects 100 Mbps operation
0 = While auto-negotiation is disabled, selects 10 Mbps operation
1 = Enables auto-negotiation
0 = Disables auto-negotiation
1 = Port is placed in a low power consumption mode. Normal operation will be allowed within 0.5 s
0 = Normal operation
1 = Isolates the port’s data path signals from the MII. The port will not respond to changes on
0 = Normal operation
the PHY to its initial state. After the reset is complete, the PHY clears this bit automatically.
The reset process will be completed within 1.3 ms of this bit being set. While the preamble is
suppressed, the management interface must not receive an ST within three MDC clock cycles
following a software reset.
allow the TXD data to be sent to the RXD data circuitry within 512 bit times. The PHY will be
isolated from the medium (no transmit or receive to the medium allowed) and the MII_COL
signal will remain de-asserted, unless this bit is set.
after PDWN and ISOL are changed to 0. During a transition to power-down mode (or if already
in power down mode), the port will respond only to management function requests through the
MI interface. All other port operations will be disabled. When power-down mode is exited, all
register values are maintained. The port will start its operation based on the register values.
MII_TXDx, MII_TXEN, and MII_TXER inputs, and it will present high impedance on
MII_TXCLK, MII_RXCLK, MII_RXDV, MII_RXER, MII_RXDx, MII_COL, and MII_CRS
outputs. The port will respond to management transactions while in isolate mode.
MC9S12NE64 Data Sheet, Rev. 1.1
Memory Map and Register Descriptions
355