mc9s12ne64 Freescale Semiconductor, Inc, mc9s12ne64 Datasheet - Page 175

no-image

mc9s12ne64

Manufacturer Part Number
mc9s12ne64
Description
Hcs12 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
mc9s12ne64CPV
Manufacturer:
RENESAS
Quantity:
21 000
Part Number:
mc9s12ne64CPV
Manufacturer:
FREESCAL
Quantity:
455
Part Number:
mc9s12ne64CPV
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc9s12ne64CPVE
Manufacturer:
ST
Quantity:
445
Part Number:
mc9s12ne64CPVE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc9s12ne64VTU
Manufacturer:
FREESCALE
Quantity:
1 831
Part Number:
mc9s12ne64VTU
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc9s12ne64VTUE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc9s12ne64VTUE
Manufacturer:
ALTERA
0
Part Number:
mc9s12ne64VTUE
Manufacturer:
FREESCALE
Quantity:
20 000
writes (0x0055 or 0x00AA) to the ARMCOP register must occur in the last 25% of the selected time-out
period. A premature write the CRG will immediately generate a reset.
As soon as the reset sequence is completed the reset generator checks the reset condition. If no clock
monitor failure is indicated and the latched state of the COP timeout is true, processing begins by fetching
the COP vector.
4.5.3
The on-chip voltage regulator detects when V
power-on reset or low voltage reset or both. As soon as a power-on reset or low voltage reset is triggered
the CRG performs a quality check on the incoming clock signal. As soon as clock quality check indicates
a valid oscillator clock signal the reset sequence starts using the oscillator clock. If after 50 check windows
the clock quality check indicated a non-valid oscillator clock the reset sequence starts using self-clock
mode.
Figure 4-26
and when the RESET pin is held low.
Freescale Semiconductor
Power-On Reset, Low Voltage Reset
and
Figure 4-27
Internal RESET
RESET
Internal POR
Internal RESET
RESET
Internal POR
Figure 4-26. RESET Pin Tied to V
show the power-up sequence for cases when the RESET pin is tied to V
Figure 4-27. RESET Pin Held Low Externally
MC9S12NE64 Data Sheet, Rev. 1.1
DD
Clock Quality Check
(no Self-Clock Mode)
Clock Quality Check
(no Self-Clock Mode)
128 SYSCLK
) (
to the MCU has reached a certain level and asserts
) (
128 SYSCLK
) (
) (
) (
) (
64 SYSCLK
DD
64 SYSCLK
(by a Pull-Up Resistor)
Resets
DD
175

Related parts for mc9s12ne64