mc9s12ne64 Freescale Semiconductor, Inc, mc9s12ne64 Datasheet - Page 48

• Manufacturer Part Number: mc9s12ne64
• Description: Hcs12 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Chapter 1 MC9S12NE64 Device Overview
1.2.3.6
PB[7:0] are general-purpose I/O pins. In MCU expanded modes of operation, these pins are used for the
multiplexed external address and data bus. PB[7:0] pins are not available in the 80-pin package version.
1.2.3.7
PE7 is a general-purpose I/O pin. During MCU expanded modes of operation, the NOACC signal, while
enabled, is used to indicate that the current bus cycle is an unused or free cycle. This signal will assert when
the CPU is not using the bus.
1.2.3.8
PE6 is a general-purpose I/O pin. It is used as an MCU operating mode select pin during reset. The state
of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the instruction
queue tracking signal IPIPE1. PE6 is an input with a pulldown device that is active only while RESET is
low. PE6 is not available in the 80-pin package version.
1.2.3.9
PE5 is a general-purpose I/O pin. It is used as an MCU operating mode select pin during reset. The state
of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the instruction
queue tracking signal IPIPE0. This pin is an input with a pull-down device that is only active while RESET
is low. PE5 is not available in the 80-pin package version.
1.2.3.10 PE4 / ECLK— Port E I/O Pin 4 / E-Clock Output
PE4 is a general-purpose I/O pin. In normal single chip mode, PE4 is configured with an active pull-up
while in reset and immediately out of reset. The pull-up can be turned off by clearing PUPEE in the PUCR
register. In all modes except normal single chip mode, the PE4 pin is initially configured as the output
connection for the internal bus clock (ECLK). ECLK is used as a timing reference and to demultiplex the
address and data in expanded modes. The ECLK frequency is equal to 1/2 the crystal frequency out of
reset. The ECLK output function depends upon the settings of the NECLK bit in the PEAR register, the
IVIS bit in the MODE register, and the ESTR bit in the EBICTL register. All clocks, including the ECLK,
are halted while the MCU is in stop mode. It is possible to configure the MCU to interface to slow external
memory. ECLK can be stretched for such accesses. The PE4 pin is initially configured as ECLK output
with stretch in all expanded modes. See the MISC register (EXSTR[1:0] bits) for more information. In
normal expanded narrow mode, the ECLK is available for use in external select decode logic or as a
constant speed clock for use in the external application system.
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PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins
PE7 / NOACC — Port E I/O Pin 7
PE6 / IPIPE1/ MODB — Port E I/O Pin 6
PE5 / IPIPE0 / MODA — Port E I/O Pin 5
MC9S12NE64 Data Sheet, Rev 1.0
Freescale Semiconductor