mc9s12ne64 Freescale Semiconductor, Inc, mc9s12ne64 Datasheet - Page 492

• Manufacturer Part Number: mc9s12ne64
• Description: Hcs12 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Chapter 18 Debug Module (DBGV1)
control (TBC) block. When PAGSEL = 01, registers DBGCAX, DBGCBX, and DBGCCX are used to
match the upper addresses as shown in
18.4.2.1.1
Read or write comparisons are useful only with TRGSEL = 0, because only opcodes should be tagged as
they are “read” from memory. RWAEN and RWBEN are ignored when TRGSEL = 1.
In full modes (“A and B” and “A and not B”) RWAEN and RWA are used to select read or write
comparisons for both comparators A and B.
the DBGCB comparison conditions. The RWBEN and RWB bits are not used and are ignored in full
modes.
18.4.2.1.2
The TRGSEL bit in DBGC1 is used to determine the triggering condition in DBG mode. TRGSEL applies
to both trigger A and B except in the event only trigger modes. By setting TRGSEL, the comparators A
and B will qualify a match with the output of opcode tracking logic and a trigger occurs before the tagged
instruction executes (tagged-type trigger). With the TRGSEL bit cleared, a comparator match forces a
trigger when the matching condition occurs (force-type trigger).
18.4.2.2
The TBC is the main controller for the DBG module. Its function is to decide whether data should be stored
in the trace buffer based on the trigger mode and the match signals from the comparator. The TBC also
determines whether a request to break the CPU should occur.
492
Trace Buffer Control (TBC)
RWAEN bit
If a tagged-type C breakpoint is set at the same address as an A/B
tagged-type trigger (including the initial entry in an inside or outside range
trigger), the C breakpoint will have priority and the trigger will not be
recognized.
Read or Write Comparison
Trigger Selection
If the TRGSEL is set, the address stored in the comparator match address
registers must be an opcode address for the trigger to occur.
0
0
1
1
1
1
Table 18-24. Read or Write Comparison Logic Table
RWA bit
x
x
0
0
1
1
MC9S12NE64 Data Sheet, Rev. 1.1
Table
Table 18-24
RW signal
18-11.
0
1
0
1
0
1
NOTE
NOTE
shows the effect for RWAEN, RWA, and RW on
No data bus compare since RW=1
No data bus compare since RW=0
Write data bus
Read data bus
Write data bus
Read data bus
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