s71ws512ne0bfwzz Meet Spansion Inc., s71ws512ne0bfwzz Datasheet - Page 23

• Manufacturer Part Number: s71ws512ne0bfwzz
• Description: Stacked Multi-chip Product Mcp Flash Memoy And Psram Cmos 1.8 Volt, Simultaneous Operation, Burst Mode Flash Memory And Pseudo-static Ram
• Manufacturer: Meet Spansion Inc.

Device Bus Operations
Legend: L = Logic 0, H = Logic 1, X = Don’t Care.
Note: Default active edge of CLK is the rising edge.
June 28, 2004 S71WS512NE0BFWZZ_00_A1
Operation
Burst Read Operations (Synchronous)
Terminate current Burst read cycle via RESET#
Asynchronous Read - Addresses Steady State
appropriate Data presented on the Data Bus
Terminate current Burst read cycle and start
Asynchronous Read - Addresses Latched
Advance Burst to next address with
Terminate current Burst read cycle
Requirements for Asynchronous Read Operation (Non-
Burst)
Load Starting Burst Address
new Burst read cycle
Asynchronous Write
Synchronous Write
Hardware Reset
Standby (CE#)
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command register
itself does not occupy any addressable memory location. The register is com-
posed of latches that store the commands, along with the address and data
information needed to execute the command. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the
function of the device.
trol levels they require, and the resulting output. The following subsections
describe each of these operations in further detail.
To read data from the memory array, the system must first assert a valid address
on A23–A0 for WS256N , while driving AVD# and CE# to V
at V
DQ15–DQ0. Since the memory array is divided into sixteen banks, each bank re-
mains enabled for read access until the command register contents are altered.
Address access time (t
output data. The chip enable access time (t
dresses and stable CE# to valid data at the outputs. The output enable access
time (t
The internal state machine is set for reading array data in asynchronous mode
upon device power-up, or after a hardware reset. This ensures that no spurious
alteration of the memory content occurs during the power transition.
IH
. The rising edge of AVD# latches the address. The data will appear on
OE
) is the delay from the falling edge of OE# to valid data at the output.
A d v a n c e
S29WSxxxN MirrorBit™ Flash Family For Multi-chip Products (MCP)
Table 2
ACC
Table 2. Device Bus Operations
) is equal to the delay from stable addresses to valid
I n f o r m a t i o n
CE#
lists the device bus operations, the inputs and con-
H
X
H
X
L
L
L
L
L
L
L
OE#
H
H
X
X
X
X
X
X
L
L
L
WE#
H
H
H
H
H
H
H
X
X
L
L
CE
) is the delay from the stable ad-
Addresses
Addr In
Addr In
Addr In
Addr In
Addr In
Addr In
X
X
X
X
X
IL
. WE# should remain
Data Out
HIGH Z
HIGH Z
HIGH Z
HIGH Z
DQ15–0
Burst
I/O
I/O
I/O
I/O
I/O
X
RESET#
H
H
H
H
H
H
H
H
H
L
L
Note)
CLK
(See
X
X
X
X
X
X
AVD#
H
X
X
X
X
L
L
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