s71ws512ne0bfwzz Meet Spansion Inc., s71ws512ne0bfwzz Datasheet - Page 51

• Manufacturer Part Number: s71ws512ne0bfwzz
• Description: Stacked Multi-chip Product Mcp Flash Memoy And Psram Cmos 1.8 Volt, Simultaneous Operation, Burst Mode Flash Memory And Pseudo-static Ram
• Manufacturer: Meet Spansion Inc.

June 28, 2004 S71WS512NE0BFWZZ_00_A1
It is recommended that the wait state command sequence be written, even if the
default wait state value is desired, to ensure the device is set as expected. A
hardware reset will set the wait state to the default setting.
Programmable Wait State
If the device is equipped with the handshaking option, the host system should set
CR13-CR11 to 010 for a clock frequency of 54 MHz or to 011 for a clock fre-
quency of 66 MHz for the system/device to execute at maximum speed.
Table 14
conditions.
Boundary Crossing Latency
If the device is operating above 66 MHz, an additional wait state must be inserted
to account for boundary crossing latency. This is done by setting CR14 to a ‘1’
(default). If the device is operating at or below 66 MHz, the additional wait state
for boundary crossing is not needed. Therefore the CR14 can be changed to a ‘0’
to remove boundary crossing latency.
Set Internal Clock Frequency
The device switches at the full frequency of the external clock up to 66 MHz when
CR9 is set to a ‘1’ (default).
Handshaking
For optimal burst mode performance, the host system must set the appropriate
number of wait states in the flash device depending on the clock frequency.
The autoselect function allows the host system to determine whether the flash
device is enabled for handshaking. See the
tion for more information.
Notes:
1. Upon power-up or hardware reset, the default setting is seven wait states.
2. RDY will default to being active with data when the Wait State Setting is set
Conditions at Address
to a total initial access cycle of 2.
CR13
0
0
0
0
1
1
1
1
Initial address (V
describes the typical number of clock cycles (wait states) for various
A d v a n c e
S29WSxxxN MirrorBit™ Flash Family For Multi-chip Products (MCP)
Table 13. Programmable Wait State Settings
CR12
Table 14. Wait States for Handshaking
0
0
1
1
0
0
1
1
IO
= 1.8 V)
I n f o r m a t i o n
CR11
0
1
0
1
0
1
0
1
"Autoselect Command
Typical No. of Clock Cycles after AVD# Low
MHz
Total Initial Access Cycles
54
4
7 (default)
Reserved
Reserved
2
3
4
5
6
Sequence" sec-
MHz
66
5
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