s71ws512ne0bfwzz Meet Spansion Inc., s71ws512ne0bfwzz Datasheet - Page 99

• Manufacturer Part Number: s71ws512ne0bfwzz
• Description: Stacked Multi-chip Product Mcp Flash Memoy And Psram Cmos 1.8 Volt, Simultaneous Operation, Burst Mode Flash Memory And Pseudo-static Ram
• Manufacturer: Meet Spansion Inc.

FUNCTIONAL DESCRIPTION (Continued)
Notes
June 28, 2004 S71WS512NE0BFWZZ_00_A1
Address
A22-A21
A20-A19
A18-A16
A14-A12
A6-A0
Pin
A15
A11
A10
A9
A8
A7
*1: A22, A21, A8, and A6 to A0 must be all "1" in any cases.
*2: It is prohibited to apply this key.
*3: If M=0, all the registers must be set with appropriate Key input at the same time.
*4: If M=1, PS must be set with appropriate Key input at the same time. Except for PS, all the other key inputs
*5: Burst Read & Single Write is not supported at WE# Single Clock Pulse Control.
Address Key
must be "1".
The address key has the following format.
Register
Name
SW
WC
BS
PS
BL
RL
VE
—
—
—
M
Write Control
Clock Edge
Function
Sequence
P r e l i m i n a r y
Latency
Length
Partial
Single
Burst
Mode
Burst
Write
Read
Valid
Size
—
—
—
128Mb pSRAM
Key
000
001
010
011
100
101
110
111
000
001
010
011
1xx
00
01
10
11
1
0
1
0
1
0
1
0
1
1
0
1
1
Description
Unused bits muse be 1
32M Partial
16M Partial
Reserved for future use
Sleep [Default]
Reserved for future use
Reserved for future use
8 words
16 words
Reserved for future use
Reserved for future use
Reserved for future use
Continuous
Synchronous Mode
(Burst Read / Write)
Asynchronous Mode[Default]
(Page Read / Normal Write)
Reserved for future use
3 clocks
4 clocks
5 clocks
Reserved for future use
Reserved for future use
Sequential
Burst Read & Burst Write
Burst Read & Single Write
Falling Clock Edge
Rising Clock Edge
Unused bits muse be 1
WE# Single Clock Pulse Control
without Write Suspend Function
WE# Level Control
with Write Suspend Function
Unused bits muse be 1
Note
*1
*2
*2
*2
*2
*2
*2
*3
*4
*2
*2
*2
*5
*1
*5
*1
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