s71ws512ne0bfwzz Meet Spansion Inc., s71ws512ne0bfwzz Datasheet - Page 63

• Manufacturer Part Number: s71ws512ne0bfwzz
• Description: Stacked Multi-chip Product Mcp Flash Memoy And Psram Cmos 1.8 Volt, Simultaneous Operation, Burst Mode Flash Memory And Pseudo-static Ram
• Manufacturer: Meet Spansion Inc.

June 28, 2004 S71WS512NE0BFWZZ_00_A1
Non-Volatile Sector Protection Command Set Definitions
Once the Password is written and verified, the Password Mode Locking Bit must
be set in order to prevent verification. The Password Program Command is only
capable of programming “0”s. Programming a “1” after a cell is programmed as
a “0” results in a time-out by the Embedded Program Algorithm™ with the cell
remaining as a “0”. The password is all F’s when shipped from the factory. All 64-
bit password combinations are valid as a password.
The Password Verify Command is used to verify the Password. The Password is
verifiable only when the Password Mode Locking Bit is not programmed. If the
Password Mode Locking Bit is programmed and the user attempts to verify the
Password, the device will always drive all F’s onto the DQ data bus.
The lower two address bits (A1–A0) are valid during the Password Read, Pass-
word Program, and Password Unlock.
The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs
can be unlocked for modification, thereby allowing the PPBs to become accessible
for modification. The exact password must be entered in order for the unlocking
function to occur. This command cannot be issued any faster than 1 µs at a time
to prevent a hacker from running through all the 64-bit combinations in an at-
tempt to correctly match a password. If the command is issued before the 1 µs
execution window for each portion of the unlock, the command will be ignored.
The Password Unlock function is accomplished by writing Password Unlock com-
mand and data to the device to perform the clearing of the PPB Lock Bit. The
password is 64 bits long. A1 and A0 are used for matching. Writing the Password
Unlock command does not need to be address order specific. An example se-
quence is starting with the lower address A1–A0= 00, followed by A1–A0= 01,
A1–A0= 10, and A1–A0= 11.
Approximately 1 µSec is required for unlocking the device after the valid 64-bit
password is given to the device. It is the responsibility of the microprocessor to
keep track of the 64-bit password as it is entered with the Password Unlock com-
mand, the order, and when to read the PPB Lock bit to confirm successful
password unlock. In order to re-lock the device into the Password Mode, the PPB
Lock Bit Set command can be re-issued.
The Password Protection Command Set Exit command must be issued after
the execution of the commands listed previously to reset the device to read
mode. Otherwise the device will hang.
Note that issuing the Password Protection Command Set Exit command re-
enables reads and writes for Bank 0.
The Non-Volatile Sector Protection Command Set permits the user to program the
Persistent Protection Bits (PPBs), erase all of the Persistent Protection Bits (PPBs),
and read the logic state of the Persistent Protection Bits (PPBs).
The Non-Volatile Sector Protection Command Set Entry command se-
quence must be issued prior to any of the following commands to enable proper
command execution.
Note that issuing the Non-Volatile Sector Protection Command Set Entry
command disables reads and writes for the bank selected. Reads within that
PPB Program Command
All PPB Erase Command
PPB Status Read Command
A d v a n c e
S29WSxxxN MirrorBit™ Flash Family For Multi-chip Products (MCP)
I n f o r m a t i o n
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