s71ws512ne0bfwzz Meet Spansion Inc., s71ws512ne0bfwzz Datasheet - Page 58

• Manufacturer Part Number: s71ws512ne0bfwzz
• Description: Stacked Multi-chip Product Mcp Flash Memoy And Psram Cmos 1.8 Volt, Simultaneous Operation, Burst Mode Flash Memory And Pseudo-static Ram
• Manufacturer: Meet Spansion Inc.

Note:
58
See the
Chip Erase Command Sequence
"Command Definition
quence, resulting in faster total programming time. The host system may also
initiate the chip erase and sector erase sequences in the unlock bypass mode. The
erase command sequences are four cycles in length instead of six cycles. The
"Command Definition
bypass command sequences.
During the unlock bypass mode, only the Read, Unlock Bypass Program, Unlock
Bypass Sector Erase, Unlock Bypass Chip Erase, and Unlock Bypass Reset com-
mands are valid. To exit the unlock bypass mode, the system must issue the two-
cycle unlock bypass reset command sequence. The first cycle must contain the
bank address and the data 90h. The second cycle need only contain the data 00h.
The bank then returns to the read mode.
The device offers accelerated program operations through the ACC input. When
the system asserts V
Bypass mode. The system may then write the two-cycle Unlock Bypass program
command sequence. The device uses the higher voltage on the ACC input to ac-
celerate the operation.
Figure 3
Program Operations table in
and
Chip erase is a six bus cycle operation or, in the unlock bypass mode, a four-cycle
operation. The chip erase command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional unlock write cycles are
then followed by the chip erase command, which in turn invokes the Embedded
Erase algorithm. The device does not require the system to preprogram prior to
Figure 21
illustrates the algorithm for the program operation. Refer to the Erase/
S29WSxxxN MirrorBit™ Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004
for timing diagrams.
Summary" section for program command sequence.
Increment Address
HH
Summary" section shows the requirements for the unlock
on this input, the device automatically enters the Unlock
Figure 3. Program Operation
A d v a n c e
“AC Characteristics—Asynchronous”
Embedded
in progress
algorithm
Program
No
Command Sequence
Write Program
Last Address?
Programming
from System
I n f o r m a t i o n
Verify Data?
Completed
Data Poll
START
Yes
Yes
No
for parameters,