s71ws512ne0bfwzz Meet Spansion Inc., s71ws512ne0bfwzz Datasheet - Page 96

• Manufacturer Part Number: s71ws512ne0bfwzz
• Description: Stacked Multi-chip Product Mcp Flash Memoy And Psram Cmos 1.8 Volt, Simultaneous Operation, Burst Mode Flash Memory And Pseudo-static Ram
• Manufacturer: Meet Spansion Inc.

FUNCTION TRUTH TABLE (Continued)
Notes:L = V
96
Next Address
Synchronous Operation (Burst Mode)
Standby
(Deselect)
Start
Address Latch
Advance
Burst Read to
Burst Read
Suspend
Advance
Burst Write to
Next Address
Burst Write
Suspend
Terminate
Burst Read
Terminate
Burst Write
Power Down
Mode
*1: Should not be kept this logic condition longer than 4ms.
*2: Power Down mode can be entered from Standby state and all DQ pins are in High-Z state.
*3: Valid clock edge shall be set on either positive or negative edge through CR Set. CLK must be started and
*4: Can be either V
*5: When device is operating in "WE# Single Clock Pulse Control" mode, WE# is don’t care once write operation
*6: Can be either V
*7: Once valid address is determined, input address must not be changed during ADV#=L.
*8: If OE#=L, output is either Invalid or High-Z depending on the level of UB# and LB# input. If WE#=L,
*9: Output is either Valid or High-Z depending on the level of UB# and LB# input.
*10: Input is either Valid or Invalid depending on the level of UB# and LB# input.
*11: Output is either High-Z or Invalid depending on the level of OE# and WE# input.
*12: Keep the level from previous cycle except for suspending on last data. Refere to "WAIT# Output Function"
*13: WAIT# output is driven in High level during write operation.
High-Z = High Impedance
IL
Please contact local FUJITSU representative for the relaxation of 4ms limitation.
Data retention depends on the selection of Partial Size.
Refer to "Power Down" in FUNCTIONAL DESCRIPTION for the details.
stable prior to memory access.
both of OE# and WE# to V
is determined by WE# Low Pulse at the beginnig of write access together with address latching. Write
suspend feature is not supported in "WE# Single Clock Pulse Control" mode
inputs are determined, they must not be changed until the end of burst.
Input is Invalid. If OE#=WE#=H, output is High-Z.
in FUNCTIONAL DESCRIPTION for the details.
, H = V
Note
IH
, X can be either V
*1
*1
*1
*1
*1
*2
IL
IL
CE2
or V
H
L
or V
IH
IH
CE#1
except for the case the both of OE# and WE# are V
H
X
L
but must be valid before Read or Write is determined. And once UB# and LB#
IL
IL
CLK
*3
*3
*3
*3
*3
X
X
X
X
or V
IH
ADV# WE#
H
,
X
X
128Mb pSRAM
= valid edge,
P r e l i m i n a r y
*4
*5
*5
H
H
H
X
X
X
X
L
OE#
*4
H
H
H
X
X
X
X
L
LB#
*6
X
X
X
= positive edge of Low pulse,
UB#
*6
X
X
X
Valid
A22-0
*7
X
X
X
IL
High-Z
High-Z
Output
High-Z
Invalid
High-Z
High-Z
High-Z
S71WS512NE0BFWZZ_00_A1 June 28, 2004
. It is prohibited to bring the
Input
Input
DQ8-1
Valid
Valid
*10
*8
*9
High-Z
High-Z
Output
High-Z
Invalid
High-Z
High-Z
High-Z
DQ16-9
Input
Input
Valid
Valid
*10
*8
*9
Output
High-Z
High-Z
High-Z
High-Z
High-Z
WAIT#
Valid
High
High
High
*11
*12
*13
*12