s71ws512ne0bfwzz Meet Spansion Inc., s71ws512ne0bfwzz Datasheet - Page 34

• Manufacturer Part Number: s71ws512ne0bfwzz
• Description: Stacked Multi-chip Product Mcp Flash Memoy And Psram Cmos 1.8 Volt, Simultaneous Operation, Burst Mode Flash Memory And Pseudo-static Ram
• Manufacturer: Meet Spansion Inc.

34
Lock Register
Hardware Data Protection Mode
The Lock Register consists of 4 bits. The Customer SecSi Sector Protection Bit is
DQ0, Persistent Protection Mode Lock Bit is DQ1, Password Protection Mode Lock
Bit is DQ2, and Persistent Sector Protection OTP Bit is DQ3. Each of these bits are
non-volatile. DQ15-DQ4 are reserved and will be 1’s.
The device offers two types of data protection at the sector level:
The write protect pin (WP#) adds a final level of hardware program and erase
protection to the outermost boot sectors. The outermost boot sectors are the sec-
tors containing both the lower and upper set of outermost sectors in a dual-boot-
configured device. When this pin is low it is not possible to change the con-
tents of these outermost sectors. These sectors generally hold system boot
code. So, the WP# pin can prevent any changes to the boot code that could over-
ride the choices made while setting up sector protection during system
initialization.
The following hardware data protection measures prevent accidental erasure or
programming, which might otherwise be caused by spurious system level signals
during V
Write Protect (WP#)
The Write Protect feature provides a hardware method of protecting the four out-
ermost sectors. This function is provided by the WP# pin and overrides the
previously discussed Sector Protection/Unprotection method.
If the system asserts V
functions in the “outermost” boot sectors. The outermost boot sectors are the
sectors containing both the lower and upper set of sectors in a dual-boot-config-
ured device.
If the system asserts V
sectors were last set to be protected or unprotected. That is, sector protection or
unprotection for these sectors depends on whether they were last protected or
unprotected.
Note that the WP# pin must not be left floating or unconnected; inconsistent be-
havior of the device may result. The WP# pin must be held stable during a
command sequence execution.
Low V
When V
tects data during V
internal program/erase circuits are disabled, and the device resets to reading
array data. Subsequent writes are ignored until V
tem must provide the proper signals to the control inputs to prevent unintentional
writes when V
When WP# is at V
When ACC is at V
DQ15-3
CC
CC
CC
1’s
is less than V
Write Inhibit
power-up and power-down transitions, or from system noise.
S29WSxxxN MirrorBit™ Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004
CC
is greater than V
CC
IL
Password Protection
IL
power-up and power-down. The command register and all
, all sectors are locked.
, the four outermost sectors are locked (device specific).
IL
IH
LKO
Mode Lock Bit
on the WP# pin, the device disables program and erase
on the WP# pin, the device reverts to whether the boot
, the device does not accept any write cycles. This pro-
Table 6. Lock Register
A d v a n c e
DQ2
LKO
.
Persistent Protection
Mode Lock Bit
I n f o r m a t i o n
DQ1
CC
is greater than V
Sector Protection Bit
Customer SecSi
LKO
DQ0
. The sys-