s71ws512ne0bfwzz Meet Spansion Inc., s71ws512ne0bfwzz Datasheet - Page 68

• Manufacturer Part Number: s71ws512ne0bfwzz
• Description: Stacked Multi-chip Product Mcp Flash Memoy And Psram Cmos 1.8 Volt, Simultaneous Operation, Burst Mode Flash Memory And Pseudo-static Ram
• Manufacturer: Meet Spansion Inc.

68
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses
latch on the rising edge of the AVD# pulse or active edge of CLK
which ever comes first.
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
PD(0) = SecSi Sector Lock Bit. PD(0), or bit[0].
PD(1) = Persistent Protection Mode Lock Bit. PD(1), or bit[1], must
be set to ‘0’ for protection while PD(2), bit[2] must be left as ‘1’.
PD(2) = Password Protection Mode Lock Bit. PD(2), or bit[2], must be
set to ‘0’ for protection while PD(1), bit[1] must be left as ‘1’.
PD(3) = Protection Mode OTP Bit. PD(3) or bit[3].
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A23–A14 for the WS256N uniquely select any
sector.
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. WS25N6 = 2230
11. The data is 0000h for an unlocked sector and 0001h for a locked
12. See the
13. The Unlock Bypass command sequence is required prior to this
14. The Unlock Bypass Reset command is required to return to
15. The system may read and program in non-erasing sectors, or
16. The Erase Resume command is valid only during the Erase
17. Command is valid when device is ready to read array data or
See
All values are in hexadecimal.
Except for the following, all bus cycles are write cycle: read
cycle, fourth through sixth cycles of the Autoselect commands,
fourth cycle of the configuration register verify and password
verify commands, and any cycle reading at RD(0) and RD(1).
Data bits DQ15–DQ8 are don’t care in command sequences,
except for RD, PD, WD, PWD, and PWD3-PWD0.
Unless otherwise noted, address bits A23–A12 for the WS256N
are don’t cares.
Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state.
The system must write the reset command to return the device
to reading array data.
No unlock or command cycles required when bank is reading
array data.
The Reset command is required to return to reading array data
(or to the erase-suspend-read mode if previously in Erase
Suspend) when a bank is in the autoselect mode, or if DQ5 goes
high (while the bank is providing status information) or
performing sector lock/unlock.
The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address. See the
"Autoselect Command
sector
command sequence.
reading array data when the bank is in the unlock bypass mode.
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
Suspend mode, and requires the bank address.
when device is in autoselect mode.
Table 2
"Autoselect Command
for description of bus operations.
Sequence" section
Sequence" section
S29WSxxxN MirrorBit™ Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004
A d v a n c e
BA = Address of the bank (A23, A22, A21, and A20 for the WS256N/
A22, A21, A20, that is being switched to autoselect mode, is in
bypass mode, or is being erased.
CR = Configuration Register data bits DQ15–DQ0.
PWD3–PWD0 = Password Data. PD3–PD0 present four 16 bit
combinations that represent the 64-bit Password
PWA = Password Address. Address bits A1 and A0 are used to select
each 16-bit portion of the 64-bit entity.
PWD = Password Data.
RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 0, if
unprotected, DQ0 = 1.
RD(1) = DQ1 protection indicator bit. If protected, DQ1 = 0, if
unprotected, DQ1 = 1.
RD(2) = DQ2 protection indicator bit. If protected, DQ2 = 0, if
unprotected, DQ2 = 1.
WBL = Write Buffer Location. Address must be within the same write
buffer page as PA.]
WC = Word Count. Number of write buffer locations to load minus 1.
18. The total number of cycles in the command sequence is
19. The entire four bus-cycle sequence must be entered for which
20. The ALL PPB ERASE command will pre-program all PPBs before
21. ACC must be at V
22. Command sequence resets device for next command after
23. Entry commands are needed to enter a specific mode to enable
24. Write Buffer Programming can be initiated after Unlock Bypass
25. If both the Persistent Protection Mode Locking Bit and the
26. The Exit command must be issued to reset the device into read
I n f o r m a t i o n
determined by the number of words written to the write buffer.
The number of cycles in the command sequence is 37 for full
page programming (32 words). Less than 32 word programming
is not recommended.
portion of the password.
erasure to prevent over-erasure of PPBs.
write-to-buffer operation.
instructions only available within that mode.
Entry.
password Protection Mode Locking Bit are set a the same time,
the command operation will abort and return the device to the
default Persistent Sector Protection Mode during 2nd Bus cycle.
Addresses will equal 00h on all future devices, but 77h for
WS256N.
mode. Otherwise the device will hang.
HH
during the entire operation of this command